arch: Make the MMU ranged translateFunction pure virtual.

The (simple) implementation in each ISAs MMU can then specify the page
size it wants, which is the page size appropriate for that ISA.

Change-Id: Ia105150601595bd6bb34379fc59508d0ffe35243
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50761
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>

src/arch/arm/mmu.hh

@@ -41,6 +41,7 @@
 #ifndef __ARCH_ARM_MMU_HH__
 #define __ARCH_ARM_MMU_HH__
 
+#include "arch/arm/page_size.hh"
 #include "arch/arm/tlb.hh"
 #include "arch/generic/mmu.hh"
 
@@ -81,6 +82,14 @@ class MMU : public BaseMMU
     TableWalker *dtbStage2Walker;
 
   public:
+    TranslationGenPtr
+    translateFunctional(Addr start, Addr size, ThreadContext *tc,
+            Mode mode, Request::Flags flags) override
+    {
+        return TranslationGenPtr(new MMUTranslationGen(
+                PageBytes, start, size, tc, this, mode, flags));
+    }
+
     enum ArmFlags
     {
         AlignmentMask = 0x7,

src/arch/generic/mmu.cc

@@ -153,15 +153,6 @@ BaseMMU::MMUTranslationGen::translate(Range &range) const
         range.paddr = req->getPaddr();
 }
 
-TranslationGenPtr
-BaseMMU::translateFunctional(Addr start, Addr size, ThreadContext *tc,
-                    BaseMMU::Mode mode, Request::Flags flags)
-{
-    return TranslationGenPtr(new MMUTranslationGen(
-                tc->getSystemPtr()->getPageBytes(), start, size, tc, this,
-                mode, flags));
-}
-
 void
 BaseMMU::takeOverFrom(BaseMMU *old_mmu)
 {

src/arch/generic/mmu.hh

@@ -146,7 +146,7 @@ class BaseMMU : public SimObject
      * instead of directly translating a specific address.
      */
     virtual TranslationGenPtr translateFunctional(Addr start, Addr size,
-            ThreadContext *tc, BaseMMU::Mode mode, Request::Flags flags);
+            ThreadContext *tc, BaseMMU::Mode mode, Request::Flags flags) = 0;
 
     virtual Fault
     finalizePhysical(const RequestPtr &req, ThreadContext *tc,

src/arch/mips/mmu.hh

@@ -39,7 +39,7 @@
 #define __ARCH_MIPS_MMU_HH__
 
 #include "arch/generic/mmu.hh"
-
+#include "arch/mips/page_size.hh"
 #include "params/MipsMMU.hh"
 
 namespace gem5
@@ -53,6 +53,14 @@ class MMU : public BaseMMU
     MMU(const MipsMMUParams &p)
       : BaseMMU(p)
     {}
+
+    TranslationGenPtr
+    translateFunctional(Addr start, Addr size, ThreadContext *tc,
+            Mode mode, Request::Flags flags) override
+    {
+        return TranslationGenPtr(new MMUTranslationGen(
+                PageBytes, start, size, tc, this, mode, flags));
+    }
 };
 
 } // namespace MipsISA

src/arch/power/mmu.hh

@@ -39,7 +39,7 @@
 #define __ARCH_POWER_MMU_HH__
 
 #include "arch/generic/mmu.hh"
-
+#include "arch/power/page_size.hh"
 #include "params/PowerMMU.hh"
 
 namespace gem5
@@ -53,6 +53,14 @@ class MMU : public BaseMMU
     MMU(const PowerMMUParams &p)
       : BaseMMU(p)
     {}
+
+    TranslationGenPtr
+    translateFunctional(Addr start, Addr size, ThreadContext *tc,
+            Mode mode, Request::Flags flags) override
+    {
+        return TranslationGenPtr(new MMUTranslationGen(
+                PageBytes, start, size, tc, this, mode, flags));
+    }
 };
 
 } // namespace PowerISA

src/arch/riscv/mmu.hh

@@ -40,6 +40,7 @@
 
 #include "arch/generic/mmu.hh"
 #include "arch/riscv/isa.hh"
+#include "arch/riscv/page_size.hh"
 #include "arch/riscv/pma_checker.hh"
 #include "arch/riscv/tlb.hh"
 
@@ -59,6 +60,14 @@ class MMU : public BaseMMU
       : BaseMMU(p), pma(p.pma_checker)
     {}
 
+    TranslationGenPtr
+    translateFunctional(Addr start, Addr size, ThreadContext *tc,
+            Mode mode, Request::Flags flags) override
+    {
+        return TranslationGenPtr(new MMUTranslationGen(
+                PageBytes, start, size, tc, this, mode, flags));
+    }
+
     PrivilegeMode
     getMemPriv(ThreadContext *tc, BaseMMU::Mode mode)
     {

src/arch/sparc/mmu.hh

@@ -39,6 +39,7 @@
 #define __ARCH_SPARC_MMU_HH__
 
 #include "arch/generic/mmu.hh"
+#include "arch/sparc/page_size.hh"
 #include "arch/sparc/tlb.hh"
 
 #include "params/SparcMMU.hh"
@@ -55,6 +56,14 @@ class MMU : public BaseMMU
       : BaseMMU(p)
     {}
 
+    TranslationGenPtr
+    translateFunctional(Addr start, Addr size, ThreadContext *tc,
+            Mode mode, Request::Flags flags) override
+    {
+        return TranslationGenPtr(new MMUTranslationGen(
+                PageBytes, start, size, tc, this, mode, flags));
+    }
+
     void
     insertItlbEntry(Addr vpn, int partition_id, int context_id, bool real,
         const PageTableEntry& PTE, int entry=-1)

src/arch/x86/mmu.hh

@@ -39,6 +39,7 @@
 #define __ARCH_X86_MMU_HH__
 
 #include "arch/generic/mmu.hh"
+#include "arch/x86/page_size.hh"
 #include "arch/x86/tlb.hh"
 
 #include "params/X86MMU.hh"
@@ -67,6 +68,14 @@ class MMU : public BaseMMU
     {
         return static_cast<TLB*>(dtb)->getWalker();
     }
+
+    TranslationGenPtr
+    translateFunctional(Addr start, Addr size, ThreadContext *tc,
+            Mode mode, Request::Flags flags) override
+    {
+        return TranslationGenPtr(new MMUTranslationGen(
+                PageBytes, start, size, tc, this, mode, flags));
+    }
 };
 
 } // namespace X86ISA