From fbe002bf125b7b9a72babbf03c1632951b49c570 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Tue, 21 Sep 2021 14:42:52 -0700 Subject: [PATCH] arch: Make the MMU ranged translateFunction pure virtual. The (simple) implementation in each ISAs MMU can then specify the page size it wants, which is the page size appropriate for that ISA. Change-Id: Ia105150601595bd6bb34379fc59508d0ffe35243 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50761 Tested-by: kokoro Maintainer: Gabe Black Reviewed-by: Daniel Carvalho --- src/arch/arm/mmu.hh | 9 +++++++++ src/arch/generic/mmu.cc | 9 --------- src/arch/generic/mmu.hh | 2 +- src/arch/mips/mmu.hh | 10 +++++++++- src/arch/power/mmu.hh | 10 +++++++++- src/arch/riscv/mmu.hh | 9 +++++++++ src/arch/sparc/mmu.hh | 9 +++++++++ src/arch/x86/mmu.hh | 9 +++++++++ 8 files changed, 55 insertions(+), 12 deletions(-) diff --git a/src/arch/arm/mmu.hh b/src/arch/arm/mmu.hh index 03660e418f..9391612593 100644 --- a/src/arch/arm/mmu.hh +++ b/src/arch/arm/mmu.hh @@ -41,6 +41,7 @@ #ifndef __ARCH_ARM_MMU_HH__ #define __ARCH_ARM_MMU_HH__ +#include "arch/arm/page_size.hh" #include "arch/arm/tlb.hh" #include "arch/generic/mmu.hh" @@ -81,6 +82,14 @@ class MMU : public BaseMMU TableWalker *dtbStage2Walker; public: + TranslationGenPtr + translateFunctional(Addr start, Addr size, ThreadContext *tc, + Mode mode, Request::Flags flags) override + { + return TranslationGenPtr(new MMUTranslationGen( + PageBytes, start, size, tc, this, mode, flags)); + } + enum ArmFlags { AlignmentMask = 0x7, diff --git a/src/arch/generic/mmu.cc b/src/arch/generic/mmu.cc index 3d1de819c3..a765228dd5 100644 --- a/src/arch/generic/mmu.cc +++ b/src/arch/generic/mmu.cc @@ -153,15 +153,6 @@ BaseMMU::MMUTranslationGen::translate(Range &range) const range.paddr = req->getPaddr(); } -TranslationGenPtr -BaseMMU::translateFunctional(Addr start, Addr size, ThreadContext *tc, - BaseMMU::Mode mode, Request::Flags flags) -{ - return TranslationGenPtr(new MMUTranslationGen( - tc->getSystemPtr()->getPageBytes(), start, size, tc, this, - mode, flags)); -} - void BaseMMU::takeOverFrom(BaseMMU *old_mmu) { diff --git a/src/arch/generic/mmu.hh b/src/arch/generic/mmu.hh index 532b591abb..d090f6de58 100644 --- a/src/arch/generic/mmu.hh +++ b/src/arch/generic/mmu.hh @@ -146,7 +146,7 @@ class BaseMMU : public SimObject * instead of directly translating a specific address. */ virtual TranslationGenPtr translateFunctional(Addr start, Addr size, - ThreadContext *tc, BaseMMU::Mode mode, Request::Flags flags); + ThreadContext *tc, BaseMMU::Mode mode, Request::Flags flags) = 0; virtual Fault finalizePhysical(const RequestPtr &req, ThreadContext *tc, diff --git a/src/arch/mips/mmu.hh b/src/arch/mips/mmu.hh index 13ea9375d3..f20c99c9c4 100644 --- a/src/arch/mips/mmu.hh +++ b/src/arch/mips/mmu.hh @@ -39,7 +39,7 @@ #define __ARCH_MIPS_MMU_HH__ #include "arch/generic/mmu.hh" - +#include "arch/mips/page_size.hh" #include "params/MipsMMU.hh" namespace gem5 @@ -53,6 +53,14 @@ class MMU : public BaseMMU MMU(const MipsMMUParams &p) : BaseMMU(p) {} + + TranslationGenPtr + translateFunctional(Addr start, Addr size, ThreadContext *tc, + Mode mode, Request::Flags flags) override + { + return TranslationGenPtr(new MMUTranslationGen( + PageBytes, start, size, tc, this, mode, flags)); + } }; } // namespace MipsISA diff --git a/src/arch/power/mmu.hh b/src/arch/power/mmu.hh index 8507e4eab9..c82ced953c 100644 --- a/src/arch/power/mmu.hh +++ b/src/arch/power/mmu.hh @@ -39,7 +39,7 @@ #define __ARCH_POWER_MMU_HH__ #include "arch/generic/mmu.hh" - +#include "arch/power/page_size.hh" #include "params/PowerMMU.hh" namespace gem5 @@ -53,6 +53,14 @@ class MMU : public BaseMMU MMU(const PowerMMUParams &p) : BaseMMU(p) {} + + TranslationGenPtr + translateFunctional(Addr start, Addr size, ThreadContext *tc, + Mode mode, Request::Flags flags) override + { + return TranslationGenPtr(new MMUTranslationGen( + PageBytes, start, size, tc, this, mode, flags)); + } }; } // namespace PowerISA diff --git a/src/arch/riscv/mmu.hh b/src/arch/riscv/mmu.hh index b0e645c594..f8afaa7380 100644 --- a/src/arch/riscv/mmu.hh +++ b/src/arch/riscv/mmu.hh @@ -40,6 +40,7 @@ #include "arch/generic/mmu.hh" #include "arch/riscv/isa.hh" +#include "arch/riscv/page_size.hh" #include "arch/riscv/pma_checker.hh" #include "arch/riscv/tlb.hh" @@ -59,6 +60,14 @@ class MMU : public BaseMMU : BaseMMU(p), pma(p.pma_checker) {} + TranslationGenPtr + translateFunctional(Addr start, Addr size, ThreadContext *tc, + Mode mode, Request::Flags flags) override + { + return TranslationGenPtr(new MMUTranslationGen( + PageBytes, start, size, tc, this, mode, flags)); + } + PrivilegeMode getMemPriv(ThreadContext *tc, BaseMMU::Mode mode) { diff --git a/src/arch/sparc/mmu.hh b/src/arch/sparc/mmu.hh index c9bb5399ad..e80f08d16f 100644 --- a/src/arch/sparc/mmu.hh +++ b/src/arch/sparc/mmu.hh @@ -39,6 +39,7 @@ #define __ARCH_SPARC_MMU_HH__ #include "arch/generic/mmu.hh" +#include "arch/sparc/page_size.hh" #include "arch/sparc/tlb.hh" #include "params/SparcMMU.hh" @@ -55,6 +56,14 @@ class MMU : public BaseMMU : BaseMMU(p) {} + TranslationGenPtr + translateFunctional(Addr start, Addr size, ThreadContext *tc, + Mode mode, Request::Flags flags) override + { + return TranslationGenPtr(new MMUTranslationGen( + PageBytes, start, size, tc, this, mode, flags)); + } + void insertItlbEntry(Addr vpn, int partition_id, int context_id, bool real, const PageTableEntry& PTE, int entry=-1) diff --git a/src/arch/x86/mmu.hh b/src/arch/x86/mmu.hh index 3f53863fcd..5dcba94e48 100644 --- a/src/arch/x86/mmu.hh +++ b/src/arch/x86/mmu.hh @@ -39,6 +39,7 @@ #define __ARCH_X86_MMU_HH__ #include "arch/generic/mmu.hh" +#include "arch/x86/page_size.hh" #include "arch/x86/tlb.hh" #include "params/X86MMU.hh" @@ -67,6 +68,14 @@ class MMU : public BaseMMU { return static_cast(dtb)->getWalker(); } + + TranslationGenPtr + translateFunctional(Addr start, Addr size, ThreadContext *tc, + Mode mode, Request::Flags flags) override + { + return TranslationGenPtr(new MMUTranslationGen( + PageBytes, start, size, tc, this, mode, flags)); + } }; } // namespace X86ISA