arch,cpu,sim: Store registers in InstRecord with InstResult.

The InstResult knows how to print registers without having to know about their actual types. Change-Id: Ib858e32a7b2fabbde4857165b9e88e87294942c8 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50254 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Gabe Black <gabe.black@gmail.com>
2021-09-11 04:19:55 -07:00
parent 81e07670b9
commit e425bcabd2
8 changed files with 55 additions and 65 deletions
--- a/src/arch/arm/insts/tme64ruby.cc
+++ b/src/arch/arm/insts/tme64ruby.cc
@@ -126,7 +126,7 @@ Tstart64::completeAcc(PacketPtr pkt, ExecContext *xc,


        uint64_t final_val = Dest64;
-        if (traceData) { traceData->setData(final_val); }
+        if (traceData) { traceData->setData(intRegClass, final_val); }
    }

    return fault;
@@ -156,7 +156,7 @@ Ttest64::execute(ExecContext *xc, Trace::InstRecord *traceData) const
    if (fault == NoFault) {
        uint64_t final_val = Dest64;
        xc->setRegOperand(this, 0, Dest64 & mask(intWidth));
-        if (traceData) { traceData->setData(final_val); }
+        if (traceData) { traceData->setData(intRegClass, final_val); }
    }

    return fault;
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -123,7 +123,7 @@ let {{
            else
                xc->setRegOperand(this, {self.dest_reg_idx}, {self.base_name});
            if (traceData)
-                traceData->setData({self.base_name});
+                traceData->setData({self.reg_class}, {self.base_name});
            '''

    class PIntReg(IntReg):
@@ -148,7 +148,7 @@ let {{
            else
                xc->setRegOperand(this, {self.dest_reg_idx}, {self.base_name});
            if (traceData)
-                traceData->setData({self.base_name});
+                traceData->setData({self.reg_class}, {self.base_name});
            '''

    class IntRegAIWPC(IntReg):
@@ -165,7 +165,7 @@ let {{
                xc->setRegOperand(this, {self.dest_reg_idx}, {self.base_name});
            {"}"}
            if (traceData)
-                traceData->setData({self.base_name});
+                traceData->setData({self.reg_class}, {self.base_name});
            '''

    class IntReg64(IntRegOp):
@@ -186,7 +186,7 @@ let {{
            xc->setRegOperand(this, {self.dest_reg_idx}, {self.base_name} &
                mask(intWidth));
            if (traceData)
-                traceData->setData({self.base_name});
+                traceData->setData({self.reg_class}, {self.base_name});
            '''
        def __init__(self, idx, id=srtNormal):
            super().__init__('ud', idx, 'IsInteger', id)
@@ -205,7 +205,7 @@ let {{
            xc->setRegOperand(this, {self.dest_reg_idx}, {self.base_name} &
                    mask(aarch64 ? 64 : 32));
            if (traceData)
-                traceData->setData({self.base_name});
+                traceData->setData({self.reg_class}, {self.base_name});
            '''

    class IntRegW64(IntReg64):
@@ -222,7 +222,7 @@ let {{
            xc->setRegOperand(this, {self.dest_reg_idx}, {self.base_name} &
                    mask(32));
            if (traceData)
-                traceData->setData({self.base_name});
+                traceData->setData({self.reg_class}, {self.base_name});
            '''

    class CCReg(CCRegOp):
@@ -248,7 +248,7 @@ let {{
            xc->setMiscReg(snsBankedIndex(dest, xc->tcBase()),
                           {self.base_name});
            if (traceData)
-                traceData->setData({self.base_name});
+                traceData->setData({self.reg_class}, {self.base_name});
            '''
        def __init__(self, idx, id=srtNormal, ctype='uw'):
            super().__init__(idx, id, ctype, (None, None, 'IsControl'))
--- a/src/arch/isa_parser/operand_types.py
+++ b/src/arch/isa_parser/operand_types.py
@@ -229,7 +229,7 @@ class RegValOperand(RegOperand):
            RegVal final_val = {reg_val};
            xc->setRegOperand(this, {self.dest_reg_idx}, final_val);
            if (traceData) {{
-                traceData->setData(final_val);
+                traceData->setData({self.reg_class}, final_val);
            }}
        }}'''

@@ -354,7 +354,7 @@ class VecRegOperand(RegOperand):
    def makeWrite(self):
        return f'''
        if (traceData) {{
-            traceData->setData(tmp_d{self.dest_reg_idx});
+            traceData->setData({self.reg_class}, &tmp_d{self.dest_reg_idx});
        }}
        '''

@@ -398,7 +398,7 @@ class VecPredRegOperand(RegOperand):
    def makeWrite(self):
        return f'''
        if (traceData) {{
-            traceData->setData(tmp_d{self.dest_reg_idx});
+            traceData->setData({self.reg_class}, &tmp_d{self.dest_reg_idx});
        }}
        '''

@@ -447,7 +447,7 @@ class ControlRegOperand(Operand):
             f'{self.dest_reg_idx}, {self.base_name});\n'
        wb += f'''
        if (traceData) {{
-            traceData->setData({self.base_name});
+            traceData->setData({self.reg_class}, {self.base_name});
        }}
        '''

--- a/src/arch/mips/isa/formats/fp.isa
+++ b/src/arch/mips/isa/formats/fp.isa
@@ -109,7 +109,7 @@ output exec {{
            if (isNan(&src_bits, 32) ) {
                mips_nan = MIPS32_QNAN;
                xc->setRegOperand(inst, 0, mips_nan);
-                if (traceData) { traceData->setData(mips_nan); }
+                if (traceData) { traceData->setData(floatRegClass, mips_nan); }
                return true;
            }
        }
@@ -139,7 +139,7 @@ output exec {{
            //Write FCSR from FloatRegFile
            cpu->tcBase()->setReg(float_reg::Fcsr, new_fcsr);

-            if (traceData) { traceData->setData(mips_nan); }
+            if (traceData) { traceData->setData(floatRegClass, mips_nan); }
            return true;
        }

--- a/src/arch/power/isa/includes.isa
+++ b/src/arch/power/isa/includes.isa
@@ -74,6 +74,7 @@ output exec {{

 #include "arch/generic/memhelpers.hh"
 #include "arch/power/faults.hh"
+#include "arch/power/regs/float.hh"
 #include "arch/power/regs/int.hh"
 #include "arch/power/regs/misc.hh"
 #include "base/condcodes.hh"
--- a/src/arch/sparc/isa/includes.isa
+++ b/src/arch/sparc/isa/includes.isa
@@ -80,6 +80,7 @@ output exec {{
 #include "arch/generic/memhelpers.hh"
 #include "arch/sparc/asi.hh"
 #include "arch/sparc/pseudo_inst_abi.hh"
+#include "arch/sparc/regs/float.hh"
 #include "base/fenv.hh"
 #include "cpu/base.hh"
 #include "cpu/exetrace.hh"
--- a/src/cpu/exetrace.cc
+++ b/src/cpu/exetrace.cc
@@ -115,18 +115,11 @@ Trace::ExeTracerRecord::traceInst(const StaticInstPtr &inst, bool ran)
            outs << "Predicated False";
        }

-        if (debug::ExecResult && data_status != DataInvalid) {
-            switch (data_status) {
-              case DataVec:
-                ccprintf(outs, " D=%s", *data.as_vec);
-                break;
-              case DataVecPred:
-                ccprintf(outs, " D=%s", *data.as_pred);
-                break;
-              default:
-                ccprintf(outs, " D=%#018x", data.as_int);
-                break;
-            }
+        if (debug::ExecResult && dataStatus != DataInvalid) {
+            if (dataStatus == DataReg)
+                ccprintf(outs, " D=%s", data.asReg.asString());
+            else
+                ccprintf(outs, " D=%#018x", data.asInt);
        }

        if (debug::ExecEffAddr && getMemValid())
--- a/src/sim/insttracer.hh
+++ b/src/sim/insttracer.hh
@@ -46,7 +46,7 @@
 #include "arch/generic/pcstate.hh"
 #include "arch/vecregs.hh"
 #include "base/types.hh"
-#include "config/the_isa.hh"
+#include "cpu/inst_res.hh"
 #include "cpu/inst_seq.hh"
 #include "cpu/static_inst.hh"
 #include "sim/sim_object.hh"
@@ -97,13 +97,14 @@ class InstRecord
     * @TODO fix this and record all destintations that an instruction writes
     * @see data_status
     */
-    union
+    union Data
    {
-        uint64_t as_int;
-        double as_double;
-        TheISA::VecRegContainer* as_vec;
-        TheISA::VecPredRegContainer* as_pred;
-    } data = {0};
+        ~Data() {}
+        Data() {}
+        uint64_t asInt = 0;
+        double asDouble;
+        InstResult asReg;
+    } data;

    /** @defgroup fetch_seq
     * This records the serial number that the instruction was fetched in.
@@ -128,9 +129,8 @@ class InstRecord
        DataInt32 = 4,
        DataInt64 = 8,
        DataDouble = 3,
-        DataVec = 5,
-        DataVecPred = 6
-    } data_status = DataInvalid;
+        DataReg = 5
+    } dataStatus = DataInvalid;

    /** @ingroup memory
     * Are the memory fields in the record valid?
@@ -166,13 +166,8 @@ class InstRecord

    virtual ~InstRecord()
    {
-        if (data_status == DataVec) {
-            assert(data.as_vec);
-            delete data.as_vec;
-        } else if (data_status == DataVecPred) {
-            assert(data.as_pred);
-            delete data.as_pred;
-        }
+        if (dataStatus == DataReg)
+            data.asReg.~InstResult();
    }

    void setWhen(Tick new_when) { when = new_when; }
@@ -189,8 +184,8 @@ class InstRecord
    void
    setData(std::array<T, N> d)
    {
-        data.as_int = d[0];
-        data_status = (DataStatus)sizeof(T);
+        data.asInt = d[0];
+        dataStatus = (DataStatus)sizeof(T);
        static_assert(sizeof(T) == DataInt8 || sizeof(T) == DataInt16 ||
                      sizeof(T) == DataInt32 || sizeof(T) == DataInt64,
                      "Type T has an unrecognized size.");
@@ -199,26 +194,26 @@ class InstRecord
    void
    setData(uint64_t d)
    {
-        data.as_int = d;
-        data_status = DataInt64;
+        data.asInt = d;
+        dataStatus = DataInt64;
    }
    void
    setData(uint32_t d)
    {
-        data.as_int = d;
-        data_status = DataInt32;
+        data.asInt = d;
+        dataStatus = DataInt32;
    }
    void
    setData(uint16_t d)
    {
-        data.as_int = d;
-        data_status = DataInt16;
+        data.asInt = d;
+        dataStatus = DataInt16;
    }
    void
    setData(uint8_t d)
    {
-        data.as_int = d;
-        data_status = DataInt8;
+        data.asInt = d;
+        dataStatus = DataInt8;
    }

    void setData(int64_t d) { setData((uint64_t)d); }
@@ -229,22 +224,22 @@ class InstRecord
    void
    setData(double d)
    {
-        data.as_double = d;
-        data_status = DataDouble;
+        data.asDouble = d;
+        dataStatus = DataDouble;
    }

    void
-    setData(TheISA::VecRegContainer& d)
+    setData(const RegClass &reg_class, RegVal val)
    {
-        data.as_vec = new TheISA::VecRegContainer(d);
-        data_status = DataVec;
+        new(&data.asReg) InstResult(reg_class, val);
+        dataStatus = DataReg;
    }

    void
-    setData(TheISA::VecPredRegContainer& d)
+    setData(const RegClass &reg_class, const void *val)
    {
-        data.as_pred = new TheISA::VecPredRegContainer(d);
-        data_status = DataVecPred;
+        new(&data.asReg) InstResult(reg_class, val);
+        dataStatus = DataReg;
    }

    void
@@ -279,9 +274,9 @@ class InstRecord
    unsigned getFlags() const { return flags; }
    bool getMemValid() const { return mem_valid; }

-    uint64_t getIntData() const { return data.as_int; }
-    double getFloatData() const { return data.as_double; }
-    int getDataStatus() const { return data_status; }
+    uint64_t getIntData() const { return data.asInt; }
+    double getFloatData() const { return data.asDouble; }
+    int getDataStatus() const { return dataStatus; }

    InstSeqNum getFetchSeq() const { return fetch_seq; }
    bool getFetchSeqValid() const { return fetch_seq_valid; }