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cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU.

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The BaseCPU type had been specializing itself based on the value of
TARGET_ISA, which is not compatible with building more than one ISA at a
time.

This change refactors the CPU models so that the BaseCPU is more
general, and the ISA specific components are added to the CPU when the
CPU types are fully specialized. For instance, The AtomicSimpleCPU has a
version called X86AtomicSimpleCPU which installs the X86 specific
aspects of the CPU.

This specialization is done in three ways.

1. The mmu parameter is assigned an instance of the architecture
specific MMU type. This provides a reasonable default, but also avoids
having having to use the ISA specific type when the parameter is
created.

2. The ISA specific types are made available as class attributes, and
the utility functions (including __init__!) in the BaseCPU class can
refer to them to get the types they need to set up the CPU at run time.

Because SimObjects have strange, unhelpful semantics as far as assigning
to their attributes, these types need to be set up in a non-SimObject
class, which is then brought in as a base of the actual SimObject type.
Because the metaclass of this other type is just "type", things work
like you would expect. The SimObject doesn't do any special processing
of base classes if they aren't also SimObjects, so these attributes
survive and are accessible using normal lookup in the BaseCPU class.

3. There are some methods like addCheckerCPU and properties like
needsTSO which have ISA specific values or behaviors. These are set in
the ISA specific subclass, where they are inherently specific to an ISA
and don't need to check TARGET_ISA.

Also, the DummyChecker which was set up for the BaseSimpleCPU which
doesn't actually do anything in either C++ or python was not carried
forward. The CPU type still exists, but it isn't installed in the
simple CPUs.

To provide backward compatibility, each ISA implements a .py file which
matches the original .py for a CPU, and the original is renamed with a
Base prefix. The ISA specific version creates an alias with the old CPU
name which maps to the ISA specific type. This way, old scripts which
refer to, for example, AtomicSimpleCPU, will get the X86AtomicSimpleCPU
if the x86 version was compiled in, the ArmAtomicSimpleCPU on arm, etc.

Unfortunately, because of how tags on PySource and by extension SimObjects
are implemented right now, if you set the tags on two SimObjects or
PySources which have the same module path, the later will overwrite the
former whether or not they both would be included. There are some
changes in review which would revamp this and make it work like you
would expect, without this central bookkeeping which has the conflict.
Since I can't use that here, I fell back to checking TARGET_ISA to
decide whether to tell SCons about those files at all.

In the long term, this mechanism should be revamped so that these
compatibility types are only available if there is exactly one ISA
compiled into gem5. After the configs have been updated and no longer
assume they can use AtomicSimpleCPU in all cases, then these types can
be deleted.

Also, because ISAs can now either provide subclasses for a CPU or not,
the CPU_MODELS variable has been removed, meaning the non-ISA
specialized versions of those CPU models will always be included in
gem5, except when building the NULL ISA.

In the future, a more granular config mechanism will hopefully be
implemented for *all* of gem5 and not just the CPUs, and these can be
conditional again in case you only need certain models, and want to
reduce build time or binary size by excluding the others.

Change-Id: I02fc3f645c551678ede46268bbea9f66c3f6c74b
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52490
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-10-29 18:40:54 -07:00
parent f4e84cd25e
commit c498d8bced
120 changed files with 1194 additions and 277 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
build_opts/ARM
View File

@@ -1,3 +1,2 @@
TARGET_ISA = 'arm'
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU'
PROTOCOL = 'CHI'

1
build_opts/ARM_MESI_Three_Level
View File

@@ -2,5 +2,4 @@
# All rights reserved.
TARGET_ISA = 'arm'
CPU_MODELS = 'TimingSimpleCPU,O3CPU'
PROTOCOL = 'MESI_Three_Level'

1
build_opts/ARM_MESI_Three_Level_HTM
View File

@@ -2,5 +2,4 @@
# All rights reserved.
TARGET_ISA = 'arm'
CPU_MODELS = 'TimingSimpleCPU,O3CPU'
PROTOCOL = 'MESI_Three_Level_HTM'

1
build_opts/ARM_MOESI_hammer
View File

@@ -2,5 +2,4 @@
# All rights reserved.
TARGET_ISA = 'arm'
CPU_MODELS = 'TimingSimpleCPU,O3CPU'
PROTOCOL = 'MOESI_hammer'

1
build_opts/GCN3_X86
View File

@@ -2,4 +2,3 @@ PROTOCOL = 'GPU_VIPER'
TARGET_ISA = 'x86'
TARGET_GPU_ISA = 'gcn3'
BUILD_GPU = True
CPU_MODELS = 'AtomicSimpleCPU,O3CPU,TimingSimpleCPU'

1
build_opts/Garnet_standalone
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@@ -1,3 +1,2 @@
TARGET_ISA = 'null'
CPU_MODELS = ''
PROTOCOL = 'Garnet_standalone'

1
build_opts/MIPS
View File

@@ -1,3 +1,2 @@
TARGET_ISA = 'mips'
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU'
PROTOCOL = 'MI_example'

1
build_opts/NULL
View File

@@ -1,3 +1,2 @@
TARGET_ISA = 'null'
CPU_MODELS = ''
PROTOCOL='MI_example'

1
build_opts/NULL_MESI_Two_Level
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@@ -1,3 +1,2 @@
TARGET_ISA = 'null'
CPU_MODELS = ''
PROTOCOL = 'MESI_Two_Level'

1
build_opts/NULL_MOESI_CMP_directory
View File

@@ -1,3 +1,2 @@
TARGET_ISA = 'null'
CPU_MODELS = ''
PROTOCOL='MOESI_CMP_directory'

1
build_opts/NULL_MOESI_CMP_token
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@@ -1,3 +1,2 @@
TARGET_ISA = 'null'
CPU_MODELS = ''
PROTOCOL='MOESI_CMP_token'

1
build_opts/NULL_MOESI_hammer
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@@ -1,3 +1,2 @@
TARGET_ISA = 'null'
CPU_MODELS = ''
PROTOCOL='MOESI_hammer'

1
build_opts/POWER
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@@ -1,3 +1,2 @@
TARGET_ISA = 'power'
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU'
PROTOCOL = 'MI_example'

1
build_opts/RISCV
View File

@@ -1,3 +1,2 @@
TARGET_ISA = 'riscv'
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,MinorCPU,O3CPU'
PROTOCOL = 'MI_example'

1
build_opts/SPARC
View File

@@ -1,3 +1,2 @@
TARGET_ISA = 'sparc'
CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU'
PROTOCOL = 'MI_example'

1
build_opts/VEGA_X86
View File

@@ -2,4 +2,3 @@ PROTOCOL = 'GPU_VIPER'
TARGET_ISA = 'x86'
TARGET_GPU_ISA = 'vega'
BUILD_GPU = True
CPU_MODELS = 'AtomicSimpleCPU,O3CPU,TimingSimpleCPU'

3
build_opts/X86
View File

@@ -1,4 +1,3 @@
TARGET_ISA = 'x86'
CPU_MODELS = 'TimingSimpleCPU,O3CPU,AtomicSimpleCPU'
PROTOCOL = 'MESI_Two_Level'
NUMBER_BITS_PER_SET = '128'
NUMBER_BITS_PER_SET = '128'

1
build_opts/X86_MESI_Two_Level
View File

@@ -1,4 +1,3 @@
TARGET_ISA = 'x86'
CPU_MODELS = 'TimingSimpleCPU,O3CPU,AtomicSimpleCPU'
PROTOCOL = 'MESI_Two_Level'
NUMBER_BITS_PER_SET = '128'

1
build_opts/X86_MI_example
View File

@@ -1,3 +1,2 @@
TARGET_ISA = 'x86'
CPU_MODELS = 'TimingSimpleCPU,O3CPU,AtomicSimpleCPU'
PROTOCOL = 'MI_example'

1
build_opts/X86_MOESI_AMD_Base
View File

@@ -1,3 +1,2 @@
PROTOCOL = 'MOESI_AMD_Base'
TARGET_ISA = 'x86'
CPU_MODELS = 'AtomicSimpleCPU,O3CPU,TimingSimpleCPU'

2
configs/common/cores/arm/HPI.py
View File

@@ -1379,7 +1379,7 @@ class HPI_L2(Cache):
write_buffers = 16
# prefetcher FIXME
class HPI(MinorCPU):
class HPI(ArmMinorCPU):
# Inherit the doc string from the module to avoid repeating it
# here.
__doc__ = __doc__

2
configs/common/cores/arm/O3_ARM_v7a.py
View File

@@ -99,7 +99,7 @@ class O3_ARM_v7a_BP(BiModeBP):
RASSize = 16
instShiftAmt = 2
class O3_ARM_v7a_3(DerivO3CPU):
class O3_ARM_v7a_3(ArmO3CPU):
LQEntries = 16
SQEntries = 16
LSQDepCheckShift = 0

2
configs/common/cores/arm/ex5_LITTLE.py
View File

@@ -88,7 +88,7 @@ class ex5_LITTLE_FUP(MinorFUPool):
ex5_LITTLE_FP(), ex5_LITTLE_MemFU(),
ex5_LITTLE_MiscFU()]
class ex5_LITTLE(MinorCPU):
class ex5_LITTLE(ArmMinorCPU):
executeFuncUnits = ex5_LITTLE_FUP()
class L1Cache(Cache):

2
configs/common/cores/arm/ex5_big.py
View File

@@ -99,7 +99,7 @@ class ex5_big_BP(BiModeBP):
RASSize = 48
instShiftAmt = 2
class ex5_big(DerivO3CPU):
class ex5_big(ArmO3CPU):
LQEntries = 16
SQEntries = 16
LSQDepCheckShift = 0

78
src/arch/arm/ArmCPU.py Normal file
View File

@@ -0,0 +1,78 @@
# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.proxy import Self
from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU
from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU
from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU
from m5.objects.BaseO3CPU import BaseO3CPU
from m5.objects.BaseO3Checker import BaseO3Checker
from m5.objects.BaseMinorCPU import BaseMinorCPU
from m5.objects.ArmDecoder import ArmDecoder
from m5.objects.ArmMMU import ArmMMU
from m5.objects.ArmInterrupts import ArmInterrupts
from m5.objects.ArmISA import ArmISA
class ArmCPU:
ArchDecoder = ArmDecoder
ArchMMU = ArmMMU
ArchInterrupts = ArmInterrupts
ArchISA = ArmISA
class ArmAtomicSimpleCPU(BaseAtomicSimpleCPU, ArmCPU):
mmu = ArmMMU()
class ArmNonCachingSimpleCPU(BaseNonCachingSimpleCPU, ArmCPU):
mmu = ArmMMU()
class ArmTimingSimpleCPU(BaseTimingSimpleCPU, ArmCPU):
mmu = ArmMMU()
class ArmO3Checker(BaseO3Checker, ArmCPU):
mmu = ArmMMU()
class ArmO3CPU(BaseO3CPU, ArmCPU):
mmu = ArmMMU()
# For x86, each CC reg is used to hold only a subset of the
# flags, so we need 4-5 times the number of CC regs as
# physical integer regs to be sure we don't run out. In
# typical real machines, CC regs are not explicitly renamed
# (it's a side effect of int reg renaming), so they should
# never be the bottleneck here.
numPhysCCRegs = Self.numPhysIntRegs * 5
def addCheckerCpu(self):
self.checker = ArmO3Checker(workload=self.workload,
exitOnError=False,
updateOnError=True,
warnOnlyOnLoadError=True)
self.checker.mmu.itb.size = self.mmu.itb.size
self.checker.mmu.dtb.size = self.mmu.dtb.size
self.checker.cpu_id = self.cpu_id
class ArmMinorCPU(BaseMinorCPU, ArmCPU):
mmu = ArmMMU()

28
src/arch/arm/AtomicSimpleCPU.py Normal file
View File

@@ -0,0 +1,28 @@
# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects.ArmCPU import ArmAtomicSimpleCPU
AtomicSimpleCPU = ArmAtomicSimpleCPU

28
src/arch/arm/MinorCPU.py Normal file
View File

@@ -0,0 +1,28 @@
# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects.ArmCPU import ArmMinorCPU
MinorCPU = ArmMinorCPU

28
src/arch/arm/NonCachingSimpleCPU.py Normal file
View File

@@ -0,0 +1,28 @@
# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects.ArmCPU import ArmNonCachingSimpleCPU
NonCachingSimpleCPU = ArmNonCachingSimpleCPU

12
src/cpu/o3/SConsopts → src/arch/arm/O3CPU.py
View File

@@ -1,7 +1,4 @@
# -*- mode:python -*-
# Copyright (c) 2006 The Regents of The University of Michigan
# All rights reserved.
# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
@@ -26,6 +23,9 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Import('*')
from m5.objects.ArmCPU import ArmO3CPU
main.Append(ALL_CPU_MODELS=['O3CPU'])
O3CPU = ArmO3CPU
# Deprecated
DerivO3CPU = O3CPU

11
src/cpu/o3/O3Checker.py → src/arch/arm/O3Checker.py
View File

@@ -1,5 +1,4 @@
# Copyright (c) 2007 The Regents of The University of Michigan
# All rights reserved.
# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
@@ -24,10 +23,6 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.params import *
from m5.objects.CheckerCPU import CheckerCPU
from m5.objects.ArmCPU import ArmO3Checker
class O3Checker(CheckerCPU):
type = 'O3Checker'
cxx_class = 'gem5::o3::Checker'
cxx_header = 'cpu/o3/checker.hh'
O3Checker = ArmO3Checker

9
src/arch/arm/SConscript
View File

@@ -112,6 +112,15 @@ SimObject('ArmTLB.py', sim_objects=['ArmTLB'], enums=['ArmLookupLevel'],
tags='arm isa')
SimObject('ArmPMU.py', sim_objects=['ArmPMU'], tags='arm isa')
SimObject('ArmCPU.py', sim_objects=[], tags='arm isa')
if env['TARGET_ISA'] == 'arm':
SimObject('AtomicSimpleCPU.py', sim_objects=[], tags='arm isa')
SimObject('TimingSimpleCPU.py', sim_objects=[], tags='arm isa')
SimObject('NonCachingSimpleCPU.py', sim_objects=[], tags='arm isa')
SimObject('O3CPU.py', sim_objects=[], tags='arm isa')
SimObject('O3Checker.py', sim_objects=[], tags='arm isa')
SimObject('MinorCPU.py', sim_objects=[], tags='arm isa')
DebugFlag('Arm', tags='arm isa')
DebugFlag('ArmTme', 'Transactional Memory Extension', tags='arm isa')
DebugFlag('Semihosting', tags='arm isa')

28
src/arch/arm/TimingSimpleCPU.py Normal file
View File

@@ -0,0 +1,28 @@
# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects.ArmCPU import ArmTimingSimpleCPU
TimingSimpleCPU = ArmTimingSimpleCPU

10
src/arch/arm/fastmodel/iris/Iris.py
View File

@@ -66,7 +66,12 @@ class IrisISA(BaseISA):
cxx_class = 'gem5::Iris::ISA'
cxx_header = 'arch/arm/fastmodel/iris/isa.hh'
class IrisBaseCPU(BaseCPU):
class IrisCPU():
ArchMMU = IrisMMU
ArchInterrupts = IrisInterrupts
ArchISA = IrisISA
class IrisBaseCPU(BaseCPU, IrisCPU):
type = 'IrisBaseCPU'
abstract = True
cxx_class = 'gem5::Iris::BaseCPU'
@@ -97,6 +102,3 @@ class IrisBaseCPU(BaseCPU):
self.isa = [ IrisISA() for i in range(self.numThreads) ]
else:
assert(len(self.isa) == int(self.numThreads))
def createInterruptController(self):
self.interrupts = [ IrisInterrupts() for i in range(self.numThreads) ]

6
src/arch/arm/kvm/BaseArmKvmCPU.py
View File

@@ -34,10 +34,14 @@
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.params import *
from m5.objects.ArmCPU import ArmCPU
from m5.objects.ArmMMU import ArmMMU
from m5.objects.BaseKvmCPU import BaseKvmCPU
class BaseArmKvmCPU(BaseKvmCPU):
class BaseArmKvmCPU(BaseKvmCPU, ArmCPU):
type = 'BaseArmKvmCPU'
cxx_header = "arch/arm/kvm/base_cpu.hh"
cxx_class = 'gem5::BaseArmKvmCPU'
abstract = True
mmu = ArmMMU()

28
src/arch/mips/AtomicSimpleCPU.py Normal file
View File

@@ -0,0 +1,28 @@
# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects.MipsCPU import MipsAtomicSimpleCPU
AtomicSimpleCPU = MipsAtomicSimpleCPU

41
src/cpu/minor/SConsopts → src/arch/mips/MipsCPU.py
View File

@@ -1,16 +1,4 @@
# -*- mode:python -*-
# Copyright (c) 2012-2014 ARM Limited
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder. You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
@@ -35,6 +23,29 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Import('*')
from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU
from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU
from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU
from m5.objects.BaseO3CPU import BaseO3CPU
from m5.objects.MipsDecoder import MipsDecoder
from m5.objects.MipsMMU import MipsMMU
from m5.objects.MipsInterrupts import MipsInterrupts
from m5.objects.MipsISA import MipsISA
main.Append(ALL_CPU_MODELS=['MinorCPU'])
class MipsCPU:
ArchDecoder = MipsDecoder
ArchMMU = MipsMMU
ArchInterrupts = MipsInterrupts
ArchISA = MipsISA
class MipsAtomicSimpleCPU(BaseAtomicSimpleCPU, MipsCPU):
mmu = MipsMMU()
class MipsNonCachingSimpleCPU(BaseNonCachingSimpleCPU, MipsCPU):
mmu = MipsMMU()
class MipsTimingSimpleCPU(BaseTimingSimpleCPU, MipsCPU):
mmu = MipsMMU()
class MipsO3CPU(BaseO3CPU, MipsCPU):
mmu = MipsMMU()

28
src/arch/mips/NonCachingSimpleCPU.py Normal file
View File

@@ -0,0 +1,28 @@
# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects.MipsCPU import MipsNonCachingSimpleCPU
NonCachingSimpleCPU = MipsNonCachingSimpleCPU

12
src/cpu/checker/SConsopts → src/arch/mips/O3CPU.py
View File

@@ -1,7 +1,4 @@
# -*- mode:python -*-
# Copyright (c) 2003-2006 The Regents of The University of Michigan
# All rights reserved.
# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
@@ -26,6 +23,9 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Import('*')
from m5.objects.MipsCPU import MipsO3CPU
main.Append(ALL_CPU_MODELS=['CheckerCPU'])
O3CPU = MipsO3CPU
# Deprecated
DerivO3CPU = O3CPU

7
src/arch/mips/SConscript
View File

@@ -51,6 +51,13 @@ SimObject('MipsSeWorkload.py', sim_objects=['MipsSEWorkload', 'MipsEmuLinux'],
tags='mips isa')
SimObject('MipsTLB.py', sim_objects=['MipsTLB'], tags='mips isa')
SimObject('MipsCPU.py', sim_objects=[], tags='mips isa')
if env['TARGET_ISA'] == 'mips':
SimObject('AtomicSimpleCPU.py', sim_objects=[], tags='mips isa')
SimObject('TimingSimpleCPU.py', sim_objects=[], tags='mips isa')
SimObject('NonCachingSimpleCPU.py', sim_objects=[], tags='mips isa')
SimObject('O3CPU.py', sim_objects=[], tags='mips isa')
DebugFlag('MipsPRA', tags='mips isa')
ISADesc('isa/main.isa', tags='mips isa')

28
src/arch/mips/TimingSimpleCPU.py Normal file
View File

@@ -0,0 +1,28 @@
# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects.MipsCPU import MipsTimingSimpleCPU
TimingSimpleCPU = MipsTimingSimpleCPU

28
src/arch/power/AtomicSimpleCPU.py Normal file
View File

@@ -0,0 +1,28 @@
# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects.PowerCPU import PowerAtomicSimpleCPU
AtomicSimpleCPU = PowerAtomicSimpleCPU

28
src/arch/power/NonCachingSimpleCPU.py Normal file
View File

@@ -0,0 +1,28 @@
# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects.PowerCPU import PowerNonCachingSimpleCPU
NonCachingSimpleCPU = PowerNonCachingSimpleCPU

12
src/cpu/simple/SConsopts → src/arch/power/O3CPU.py
View File

@@ -1,7 +1,4 @@
# -*- mode:python -*-
# Copyright (c) 2006 The Regents of The University of Michigan
# All rights reserved.
# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
@@ -26,6 +23,9 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Import('*')
from m5.objects.PowerCPU import PowerO3CPU
main.Append(ALL_CPU_MODELS=['AtomicSimpleCPU', 'TimingSimpleCPU'])
O3CPU = PowerO3CPU
# Deprecated
DerivO3CPU = O3CPU

51
src/arch/power/PowerCPU.py Normal file
View File

@@ -0,0 +1,51 @@
# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU
from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU
from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU
from m5.objects.BaseO3CPU import BaseO3CPU
from m5.objects.PowerDecoder import PowerDecoder
from m5.objects.PowerMMU import PowerMMU
from m5.objects.PowerInterrupts import PowerInterrupts
from m5.objects.PowerISA import PowerISA
class PowerCPU:
ArchDecoder = PowerDecoder
ArchMMU = PowerMMU
ArchInterrupts = PowerInterrupts
ArchISA = PowerISA
class PowerAtomicSimpleCPU(BaseAtomicSimpleCPU, PowerCPU):
mmu = PowerMMU()
class PowerNonCachingSimpleCPU(BaseNonCachingSimpleCPU, PowerCPU):
mmu = PowerMMU()
class PowerTimingSimpleCPU(BaseTimingSimpleCPU, PowerCPU):
mmu = PowerMMU()
class PowerO3CPU(BaseO3CPU, PowerCPU):
mmu = PowerMMU()

7
src/arch/power/SConscript
View File

@@ -55,6 +55,13 @@ SimObject('PowerSeWorkload.py', sim_objects=[
'PowerSEWorkload', 'PowerEmuLinux'], tags='power isa')
SimObject('PowerTLB.py', sim_objects=['PowerTLB'], tags='power isa')
SimObject('PowerCPU.py', sim_objects=[], tags='power isa')
if env['TARGET_ISA'] == 'power':
SimObject('AtomicSimpleCPU.py', sim_objects=[], tags='power isa')
SimObject('TimingSimpleCPU.py', sim_objects=[], tags='power isa')
SimObject('NonCachingSimpleCPU.py', sim_objects=[], tags='power isa')
SimObject('O3CPU.py', sim_objects=[], tags='power isa')
DebugFlag('Power', tags='power isa')
ISADesc('isa/main.isa', tags='power isa')

28
src/arch/power/TimingSimpleCPU.py Normal file
View File

@@ -0,0 +1,28 @@
# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects.PowerCPU import PowerTimingSimpleCPU
TimingSimpleCPU = PowerTimingSimpleCPU

28
src/arch/riscv/AtomicSimpleCPU.py Normal file
View File

@@ -0,0 +1,28 @@
# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects.RiscvCPU import RiscvAtomicSimpleCPU
AtomicSimpleCPU = RiscvAtomicSimpleCPU

28
src/arch/riscv/MinorCPU.py Normal file
View File

@@ -0,0 +1,28 @@
# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects.RiscvCPU import RiscvMinorCPU
MinorCPU = RiscvMinorCPU

28
src/arch/riscv/NonCachingSimpleCPU.py Normal file
View File

@@ -0,0 +1,28 @@
# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects.RiscvCPU import RiscvNonCachingSimpleCPU
NonCachingSimpleCPU = RiscvNonCachingSimpleCPU

12
src/cpu/SConsopts → src/arch/riscv/O3CPU.py
View File

@@ -1,4 +1,4 @@
# Copyright 2020 Google, Inc.
# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
@@ -23,9 +23,9 @@
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Import('*')
from m5.objects.RiscvCPU import RiscvO3CPU
def add_cpu_models_var():
sticky_vars.Add(ListVariable('CPU_MODELS', 'CPU models', [],
sorted(set(main.Split('${ALL_CPU_MODELS}')))))
AfterSConsopts(add_cpu_models_var)
O3CPU = RiscvO3CPU
# Deprecated
DerivO3CPU = O3CPU

55
src/arch/riscv/RiscvCPU.py Normal file
View File

@@ -0,0 +1,55 @@
# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU
from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU
from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU
from m5.objects.BaseO3CPU import BaseO3CPU
from m5.objects.BaseMinorCPU import BaseMinorCPU
from m5.objects.RiscvDecoder import RiscvDecoder
from m5.objects.RiscvMMU import RiscvMMU
from m5.objects.RiscvInterrupts import RiscvInterrupts
from m5.objects.RiscvISA import RiscvISA
class RiscvCPU:
ArchDecoder = RiscvDecoder
ArchMMU = RiscvMMU
ArchInterrupts = RiscvInterrupts
ArchISA = RiscvISA
class RiscvAtomicSimpleCPU(BaseAtomicSimpleCPU, RiscvCPU):
mmu = RiscvMMU()
class RiscvNonCachingSimpleCPU(BaseNonCachingSimpleCPU, RiscvCPU):
mmu = RiscvMMU()
class RiscvTimingSimpleCPU(BaseTimingSimpleCPU, RiscvCPU):
mmu = RiscvMMU()
class RiscvO3CPU(BaseO3CPU, RiscvCPU):
mmu = RiscvMMU()
class RiscvMinorCPU(BaseMinorCPU, RiscvCPU):
mmu = RiscvMMU()

8
src/arch/riscv/SConscript
View File

@@ -74,6 +74,14 @@ SimObject('RiscvSeWorkload.py', sim_objects=[
SimObject('RiscvTLB.py', sim_objects=['RiscvPagetableWalker', 'RiscvTLB'],
tags='riscv isa')
SimObject('RiscvCPU.py', sim_objects=[], tags='riscv isa')
if env['TARGET_ISA'] == 'riscv':
SimObject('AtomicSimpleCPU.py', sim_objects=[], tags='riscv isa')
SimObject('TimingSimpleCPU.py', sim_objects=[], tags='riscv isa')
SimObject('NonCachingSimpleCPU.py', sim_objects=[], tags='riscv isa')
SimObject('O3CPU.py', sim_objects=[], tags='riscv isa')
SimObject('MinorCPU.py', sim_objects=[], tags='riscv isa')
DebugFlag('RiscvMisc', tags='riscv isa')
DebugFlag('PMP', tags='riscv isa')

28
src/arch/riscv/TimingSimpleCPU.py Normal file
View File

@@ -0,0 +1,28 @@
# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects.RiscvCPU import RiscvTimingSimpleCPU
TimingSimpleCPU = RiscvTimingSimpleCPU

28
src/arch/sparc/AtomicSimpleCPU.py Normal file
View File

@@ -0,0 +1,28 @@
# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects.SparcCPU import SparcAtomicSimpleCPU
AtomicSimpleCPU = SparcAtomicSimpleCPU

28
src/arch/sparc/NonCachingSimpleCPU.py Normal file
View File

@@ -0,0 +1,28 @@
# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects.SparcCPU import SparcNonCachingSimpleCPU
NonCachingSimpleCPU = SparcNonCachingSimpleCPU

31
src/arch/sparc/O3CPU.py Normal file
View File

@@ -0,0 +1,31 @@
# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects.SparcCPU import SparcO3CPU
O3CPU = SparcO3CPU
# Deprecated
DerivO3CPU = O3CPU

7
src/arch/sparc/SConscript
View File

@@ -56,6 +56,13 @@ SimObject('SparcSeWorkload.py', sim_objects=[
'SparcSEWorkload', 'SparcEmuLinux'], tags='sparc isa')
SimObject('SparcTLB.py', sim_objects=['SparcTLB'], tags='sparc isa')
SimObject('SparcCPU.py', sim_objects=[], tags='sparc isa')
if env['TARGET_ISA'] == 'sparc':
SimObject('AtomicSimpleCPU.py', sim_objects=[], tags='sparc isa')
SimObject('TimingSimpleCPU.py', sim_objects=[], tags='sparc isa')
SimObject('NonCachingSimpleCPU.py', sim_objects=[], tags='sparc isa')
SimObject('O3CPU.py', sim_objects=[], tags='sparc isa')
DebugFlag('Sparc', "Generic SPARC ISA stuff", tags='sparc isa')
DebugFlag('RegisterWindows', "Register window manipulation", tags='sparc isa')

51
src/arch/sparc/SparcCPU.py Normal file
View File

@@ -0,0 +1,51 @@
# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU
from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU
from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU
from m5.objects.BaseO3CPU import BaseO3CPU
from m5.objects.SparcDecoder import SparcDecoder
from m5.objects.SparcMMU import SparcMMU
from m5.objects.SparcInterrupts import SparcInterrupts
from m5.objects.SparcISA import SparcISA
class SparcCPU:
ArchDecoder = SparcDecoder
ArchMMU = SparcMMU
ArchInterrupts = SparcInterrupts
ArchISA = SparcISA
class SparcAtomicSimpleCPU(BaseAtomicSimpleCPU, SparcCPU):
mmu = SparcMMU()
class SparcNonCachingSimpleCPU(BaseNonCachingSimpleCPU, SparcCPU):
mmu = SparcMMU()
class SparcTimingSimpleCPU(BaseTimingSimpleCPU, SparcCPU):
mmu = SparcMMU()
class SparcO3CPU(BaseO3CPU, SparcCPU):
mmu = SparcMMU()

28
src/arch/sparc/TimingSimpleCPU.py Normal file
View File

@@ -0,0 +1,28 @@
# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects.SparcCPU import SparcTimingSimpleCPU
TimingSimpleCPU = SparcTimingSimpleCPU

28
src/arch/x86/AtomicSimpleCPU.py Normal file
View File

@@ -0,0 +1,28 @@
# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects.X86CPU import X86AtomicSimpleCPU
AtomicSimpleCPU = X86AtomicSimpleCPU

28
src/arch/x86/NonCachingSimpleCPU.py Normal file
View File

@@ -0,0 +1,28 @@
# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects.X86CPU import X86NonCachingSimpleCPU
NonCachingSimpleCPU = X86NonCachingSimpleCPU

31
src/arch/x86/O3CPU.py Normal file
View File

@@ -0,0 +1,31 @@
# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects.X86CPU import X86O3CPU
O3CPU = X86O3CPU
# Deprecated
DerivO3CPU = O3CPU

7
src/arch/x86/SConscript
View File

@@ -72,6 +72,13 @@ SimObject('X86NativeTrace.py', sim_objects=['X86NativeTrace'], tags='x86 isa')
SimObject('X86TLB.py', sim_objects=['X86PagetableWalker', 'X86TLB'],
tags='x86 isa')
SimObject('X86CPU.py', sim_objects=[], tags='x86 isa')
if env['TARGET_ISA'] == 'x86':
SimObject('AtomicSimpleCPU.py', sim_objects=[], tags='x86 isa')
SimObject('TimingSimpleCPU.py', sim_objects=[], tags='x86 isa')
SimObject('NonCachingSimpleCPU.py', sim_objects=[], tags='x86 isa')
SimObject('O3CPU.py', sim_objects=[], tags='x86 isa')
DebugFlag('LocalApic', "Local APIC debugging", tags='x86 isa')
DebugFlag('X86', "Generic X86 ISA debugging", tags='x86 isa')
DebugFlag('ACPI', "ACPI debugging", tags='x86 isa')

28
src/arch/x86/TimingSimpleCPU.py Normal file
View File

@@ -0,0 +1,28 @@
# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.objects.X86CPU import X86TimingSimpleCPU
TimingSimpleCPU = X86TimingSimpleCPU

62
src/arch/x86/X86CPU.py Normal file
View File

@@ -0,0 +1,62 @@
# Copyright 2021 Google, Inc.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.proxy import Self
from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU
from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU
from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU
from m5.objects.BaseO3CPU import BaseO3CPU
from m5.objects.X86Decoder import X86Decoder
from m5.objects.X86MMU import X86MMU
from m5.objects.X86LocalApic import X86LocalApic
from m5.objects.X86ISA import X86ISA
class X86CPU:
ArchDecoder = X86Decoder
ArchMMU = X86MMU
ArchInterrupts = X86LocalApic
ArchISA = X86ISA
class X86AtomicSimpleCPU(BaseAtomicSimpleCPU, X86CPU):
mmu = X86MMU()
class X86NonCachingSimpleCPU(BaseNonCachingSimpleCPU, X86CPU):
mmu = X86MMU()
class X86TimingSimpleCPU(BaseTimingSimpleCPU, X86CPU):
mmu = X86MMU()
class X86O3CPU(BaseO3CPU, X86CPU):
mmu = X86MMU()
needsTSO = True
# For x86, each CC reg is used to hold only a subset of the
# flags, so we need 4-5 times the number of CC regs as
# physical integer regs to be sure we don't run out. In
# typical real machines, CC regs are not explicitly renamed
# (it's a side effect of int reg renaming), so they should
# never be the bottleneck here.
numPhysCCRegs = Self.numPhysIntRegs * 5

6
src/arch/x86/kvm/X86KvmCPU.py
View File

@@ -28,12 +28,16 @@ from m5.params import *
from m5.SimObject import *
from m5.objects.BaseKvmCPU import BaseKvmCPU
from m5.objects.X86CPU import X86CPU
from m5.objects.X86MMU import X86MMU
class X86KvmCPU(BaseKvmCPU):
class X86KvmCPU(BaseKvmCPU, X86CPU):
type = 'X86KvmCPU'
cxx_header = "arch/x86/kvm/x86_cpu.hh"
cxx_class = 'gem5::X86KvmCPU'
mmu = X86MMU()
cxx_exports = [
PyBindMethod("dumpFpuRegs"),
PyBindMethod("dumpIntRegs"),

56
src/cpu/BaseCPU.py
View File

@@ -56,41 +56,6 @@ from m5.objects.Platform import Platform
default_tracer = ExeTracer()
if buildEnv['TARGET_ISA'] == 'sparc':
from m5.objects.SparcMMU import SparcMMU as ArchMMU
from m5.objects.SparcInterrupts import SparcInterrupts as ArchInterrupts
from m5.objects.SparcISA import SparcISA as ArchISA
from m5.objects.SparcDecoder import SparcDecoder as ArchDecoder
elif buildEnv['TARGET_ISA'] == 'x86':
from m5.objects.X86MMU import X86MMU as ArchMMU
from m5.objects.X86LocalApic import X86LocalApic as ArchInterrupts
from m5.objects.X86ISA import X86ISA as ArchISA
from m5.objects.X86Decoder import X86Decoder as ArchDecoder
elif buildEnv['TARGET_ISA'] == 'mips':
from m5.objects.MipsMMU import MipsMMU as ArchMMU
from m5.objects.MipsInterrupts import MipsInterrupts as ArchInterrupts
from m5.objects.MipsISA import MipsISA as ArchISA
from m5.objects.MipsDecoder import MipsDecoder as ArchDecoder
elif buildEnv['TARGET_ISA'] == 'arm':
from m5.objects.ArmMMU import ArmMMU as ArchMMU
from m5.objects.ArmInterrupts import ArmInterrupts as ArchInterrupts
from m5.objects.ArmISA import ArmISA as ArchISA
from m5.objects.ArmDecoder import ArmDecoder as ArchDecoder
elif buildEnv['TARGET_ISA'] == 'power':
from m5.objects.PowerMMU import PowerMMU as ArchMMU
from m5.objects.PowerInterrupts import PowerInterrupts as ArchInterrupts
from m5.objects.PowerISA import PowerISA as ArchISA
from m5.objects.PowerDecoder import PowerDecoder as ArchDecoder
elif buildEnv['TARGET_ISA'] == 'riscv':
from m5.objects.RiscvMMU import RiscvMMU as ArchMMU
from m5.objects.RiscvInterrupts import RiscvInterrupts as ArchInterrupts
from m5.objects.RiscvISA import RiscvISA as ArchISA
from m5.objects.RiscvDecoder import RiscvDecoder as ArchDecoder
else:
print("Don't know what object types to use for ISA %s" %
buildEnv['TARGET_ISA'])
sys.exit(1)
class BaseCPU(ClockedObject):
type = 'BaseCPU'
abstract = True
@@ -155,7 +120,7 @@ class BaseCPU(ClockedObject):
workload = VectorParam.Process([], "processes to run")
mmu = Param.BaseMMU(ArchMMU(), "CPU memory management unit")
mmu = Param.BaseMMU(NULL, "CPU memory management unit")
interrupts = VectorParam.BaseInterrupts([], "Interrupt Controller")
isa = VectorParam.BaseISA([], "ISA instance")
decoder = VectorParam.InstDecoder([], "Decoder instance")
@@ -183,7 +148,8 @@ class BaseCPU(ClockedObject):
_uncached_interrupt_request_ports = []
def createInterruptController(self):
self.interrupts = [ArchInterrupts() for i in range(self.numThreads)]
self.interrupts = [
self.ArchInterrupts() for i in range(self.numThreads)]
def connectCachedPorts(self, in_ports):
for p in self._cached_ports:
@@ -217,13 +183,13 @@ class BaseCPU(ClockedObject):
self._cached_ports += ["itb_walker_cache.mem_side", \
"dtb_walker_cache.mem_side"]
else:
self._cached_ports += ArchMMU.walkerPorts()
self._cached_ports += self.ArchMMU.walkerPorts()
# Checker doesn't need its own tlb caches because it does
# functional accesses only
if self.checker != NULL:
self._cached_ports += [ "checker." + port
for port in ArchMMU.walkerPorts() ]
for port in self.ArchMMU.walkerPorts() ]
def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc=None, dwc=None,
xbar=None):
@@ -238,14 +204,14 @@ class BaseCPU(ClockedObject):
# If no ISAs have been created, assume that the user wants the
# default ISA.
if len(self.isa) == 0:
self.isa = list([ ArchISA() for i in range(self.numThreads) ])
self.isa = [ self.ArchISA() for i in range(self.numThreads) ]
else:
if len(self.isa) != int(self.numThreads):
raise RuntimeError("Number of ISA instances doesn't "
"match thread count")
if len(self.decoder) != 0:
raise RuntimeError("Decoders should not be set up manually")
self.decoder = list([ ArchDecoder(isa=isa) for isa in self.isa ])
self.decoder = list([ self.ArchDecoder(isa=isa) for isa in self.isa ])
if self.checker != NULL:
self.checker.createThreads()
@@ -308,18 +274,18 @@ class BaseCPU(ClockedObject):
super().__init__(**kwargs)
self.power_state.possible_states=['ON', 'CLK_GATED', 'OFF']
self._cached_ports = self._cached_ports + ArchMMU.walkerPorts()
self._cached_ports = self._cached_ports + self.ArchMMU.walkerPorts()
# Practically speaking, these ports will exist on the x86 interrupt
# controller class.
if "pio" in ArchInterrupts._ports:
if "pio" in self.ArchInterrupts._ports:
self._uncached_interrupt_response_ports = \
self._uncached_interrupt_response_ports + ["interrupts[0].pio"]
if "int_responder" in ArchInterrupts._ports:
if "int_responder" in self.ArchInterrupts._ports:
self._uncached_interrupt_response_ports = \
self._uncached_interrupt_response_ports + [
"interrupts[0].int_responder"]
if "int_requestor" in ArchInterrupts._ports:
if "int_requestor" in self.ArchInterrupts._ports:
self._uncached_interrupt_request_ports = \
self._uncached_interrupt_request_ports + [
"interrupts[0].int_requestor"]

4
src/cpu/minor/MinorCPU.py → src/cpu/minor/BaseMinorCPU.py
View File

@@ -184,8 +184,8 @@ class MinorDefaultFUPool(MinorFUPool):
class ThreadPolicy(Enum): vals = ['SingleThreaded', 'RoundRobin', 'Random']
class MinorCPU(BaseCPU):
type = 'MinorCPU'
class BaseMinorCPU(BaseCPU):
type = 'BaseMinorCPU'
cxx_header = "cpu/minor/cpu.hh"
cxx_class = 'gem5::MinorCPU'

6
src/cpu/minor/SConscript
View File

@@ -40,10 +40,10 @@
Import('*')
if 'MinorCPU' in env['CPU_MODELS']:
SimObject('MinorCPU.py', sim_objects=[
if env['TARGET_ISA'] != 'null':
SimObject('BaseMinorCPU.py', sim_objects=[
'MinorOpClass', 'MinorOpClassSet', 'MinorFUTiming', 'MinorFU',
'MinorFUPool', 'MinorCPU'],
'MinorFUPool', 'BaseMinorCPU'],
enums=['ThreadPolicy'])
Source('activity.cc')

2
src/cpu/minor/cpu.cc
View File

@@ -47,7 +47,7 @@
namespace gem5
{
MinorCPU::MinorCPU(const MinorCPUParams &params) :
MinorCPU::MinorCPU(const BaseMinorCPUParams &params) :
BaseCPU(params),
threadPolicy(params.threadPolicy),
stats(this)

4
src/cpu/minor/cpu.hh
View File

@@ -51,7 +51,7 @@
#include "cpu/minor/stats.hh"
#include "cpu/simple_thread.hh"
#include "enums/ThreadPolicy.hh"
#include "params/MinorCPU.hh"
#include "params/BaseMinorCPU.hh"
namespace gem5
{
@@ -126,7 +126,7 @@ class MinorCPU : public BaseCPU
Port &getInstPort() override;
public:
MinorCPU(const MinorCPUParams &params);
MinorCPU(const BaseMinorCPUParams &params);
~MinorCPU();

2
src/cpu/minor/decode.cc
View File

@@ -51,7 +51,7 @@ namespace minor
Decode::Decode(const std::string &name,
MinorCPU &cpu_,
const MinorCPUParams &params,
const BaseMinorCPUParams &params,
Latch<ForwardInstData>::Output inp_,
Latch<ForwardInstData>::Input out_,
std::vector<InputBuffer<ForwardInstData>> &next_stage_input_buffer) :

2
src/cpu/minor/decode.hh
View File

@@ -141,7 +141,7 @@ class Decode : public Named
public:
Decode(const std::string &name,
MinorCPU &cpu_,
const MinorCPUParams &params,
const BaseMinorCPUParams &params,
Latch<ForwardInstData>::Output inp_,
Latch<ForwardInstData>::Input out_,
std::vector<InputBuffer<ForwardInstData>> &next_stage_input_buffer);

2
src/cpu/minor/execute.cc
View File

@@ -63,7 +63,7 @@ namespace minor
Execute::Execute(const std::string &name_,
MinorCPU &cpu_,
const MinorCPUParams &params,
const BaseMinorCPUParams &params,
Latch<ForwardInstData>::Output inp_,
Latch<BranchData>::Input out_) :
Named(name_),

2
src/cpu/minor/execute.hh
View File

@@ -326,7 +326,7 @@ class Execute : public Named
public:
Execute(const std::string &name_,
MinorCPU &cpu_,
const MinorCPUParams &params,
const BaseMinorCPUParams &params,
Latch<ForwardInstData>::Output inp_,
Latch<BranchData>::Input out_);

2
src/cpu/minor/fetch1.cc
View File

@@ -60,7 +60,7 @@ namespace minor
Fetch1::Fetch1(const std::string &name_,
MinorCPU &cpu_,
const MinorCPUParams &params,
const BaseMinorCPUParams &params,
Latch<BranchData>::Output inp_,
Latch<ForwardLineData>::Input out_,
Latch<BranchData>::Output prediction_,

2
src/cpu/minor/fetch1.hh
View File

@@ -386,7 +386,7 @@ class Fetch1 : public Named
public:
Fetch1(const std::string &name_,
MinorCPU &cpu_,
const MinorCPUParams &params,
const BaseMinorCPUParams &params,
Latch<BranchData>::Output inp_,
Latch<ForwardLineData>::Input out_,
Latch<BranchData>::Output prediction_,

2
src/cpu/minor/fetch2.cc
View File

@@ -58,7 +58,7 @@ namespace minor
Fetch2::Fetch2(const std::string &name,
MinorCPU &cpu_,
const MinorCPUParams &params,
const BaseMinorCPUParams &params,
Latch<ForwardLineData>::Output inp_,
Latch<BranchData>::Output branchInp_,
Latch<BranchData>::Input predictionOut_,

4
src/cpu/minor/fetch2.hh
View File

@@ -52,7 +52,7 @@
#include "cpu/minor/cpu.hh"
#include "cpu/minor/pipe_data.hh"
#include "cpu/pred/bpred_unit.hh"
#include "params/MinorCPU.hh"
#include "params/BaseMinorCPU.hh"
namespace gem5
{
@@ -201,7 +201,7 @@ class Fetch2 : public Named
public:
Fetch2(const std::string &name,
MinorCPU &cpu_,
const MinorCPUParams &params,
const BaseMinorCPUParams &params,
Latch<ForwardLineData>::Output inp_,
Latch<BranchData>::Output branchInp_,
Latch<BranchData>::Input predictionOut_,

2
src/cpu/minor/pipeline.cc
View File

@@ -55,7 +55,7 @@ GEM5_DEPRECATED_NAMESPACE(Minor, minor);
namespace minor
{
Pipeline::Pipeline(MinorCPU &cpu_, const MinorCPUParams &params) :
Pipeline::Pipeline(MinorCPU &cpu_, const BaseMinorCPUParams &params) :
Ticked(cpu_, &(cpu_.BaseCPU::baseStats.numCycles)),
cpu(cpu_),
allow_idling(params.enableIdling),

4
src/cpu/minor/pipeline.hh
View File

@@ -51,7 +51,7 @@
#include "cpu/minor/execute.hh"
#include "cpu/minor/fetch1.hh"
#include "cpu/minor/fetch2.hh"
#include "params/MinorCPU.hh"
#include "params/BaseMinorCPU.hh"
#include "sim/ticked_object.hh"
namespace gem5
@@ -109,7 +109,7 @@ class Pipeline : public Ticked
bool needToSignalDrained;
public:
Pipeline(MinorCPU &cpu_, const MinorCPUParams &params);
Pipeline(MinorCPU &cpu_, const BaseMinorCPUParams &params);
public:
/** Wake up the Fetch unit. This is needed on thread activation esp.

61
src/cpu/o3/O3CPU.py → src/cpu/o3/BaseO3CPU.py
View File

@@ -42,7 +42,7 @@ from m5.proxy import *
from m5.objects.BaseCPU import BaseCPU
from m5.objects.FUPool import *
from m5.objects.O3Checker import O3Checker
#from m5.objects.O3Checker import O3Checker
from m5.objects.BranchPredictor import *
class SMTFetchPolicy(ScopedEnum):
@@ -54,8 +54,8 @@ class SMTQueuePolicy(ScopedEnum):
class CommitPolicy(ScopedEnum):
vals = [ 'RoundRobin', 'OldestReady' ]
class O3CPU(BaseCPU):
type = 'O3CPU'
class BaseO3CPU(BaseCPU):
type = 'BaseO3CPU'
cxx_class = 'gem5::o3::CPU'
cxx_header = 'cpu/o3/dyn_inst.hh'
@@ -120,40 +120,36 @@ class O3CPU(BaseCPU):
trapLatency = Param.Cycles(13, "Trap latency")
fetchTrapLatency = Param.Cycles(1, "Fetch trap latency")
backComSize = Param.Unsigned(5, "Time buffer size for backwards communication")
forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication")
backComSize = Param.Unsigned(5,
"Time buffer size for backwards communication")
forwardComSize = Param.Unsigned(5,
"Time buffer size for forward communication")
LQEntries = Param.Unsigned(32, "Number of load queue entries")
SQEntries = Param.Unsigned(32, "Number of store queue entries")
LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check")
LSQDepCheckShift = Param.Unsigned(4,
"Number of places to shift addr before check")
LSQCheckLoads = Param.Bool(True,
"Should dependency violations be checked for loads & stores or just stores")
"Should dependency violations be checked for "
"loads & stores or just stores")
store_set_clear_period = Param.Unsigned(250000,
"Number of load/store insts before the dep predictor should be invalidated")
"Number of load/store insts before the dep predictor "
"should be invalidated")
LFSTSize = Param.Unsigned(1024, "Last fetched store table size")
SSITSize = Param.Unsigned(1024, "Store set ID table size")
numRobs = Param.Unsigned(1, "Number of Reorder Buffers");
numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers")
numPhysIntRegs = Param.Unsigned(256,
"Number of physical integer registers")
numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point "
"registers")
# most ISAs don't use condition-code regs, so default is 0
_defaultNumPhysCCRegs = 0
if buildEnv['TARGET_ISA'] in ('arm','x86'):
# For x86, each CC reg is used to hold only a subset of the
# flags, so we need 4-5 times the number of CC regs as
# physical integer regs to be sure we don't run out. In
# typical real machines, CC regs are not explicitly renamed
# (it's a side effect of int reg renaming), so they should
# never be the bottleneck here.
_defaultNumPhysCCRegs = Self.numPhysIntRegs * 5
numPhysVecRegs = Param.Unsigned(256, "Number of physical vector "
"registers")
numPhysVecPredRegs = Param.Unsigned(32, "Number of physical predicate "
"registers")
numPhysCCRegs = Param.Unsigned(_defaultNumPhysCCRegs,
"Number of physical cc registers")
# most ISAs don't use condition-code regs, so default is 0
numPhysCCRegs = Param.Unsigned(0, "Number of physical cc registers")
numIQEntries = Param.Unsigned(64, "Number of instruction queue entries")
numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries")
@@ -173,25 +169,4 @@ class O3CPU(BaseCPU):
branchPred = Param.BranchPredictor(TournamentBP(numThreads =
Parent.numThreads),
"Branch Predictor")
needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86',
"Enable TSO Memory model")
def addCheckerCpu(self):
if buildEnv['TARGET_ISA'] in ['arm']:
from m5.objects.ArmMMU import ArmMMU
self.checker = O3Checker(workload=self.workload,
exitOnError=False,
updateOnError=True,
warnOnlyOnLoadError=True)
self.checker.mmu = ArmMMU()
self.checker.mmu.itb.size = self.mmu.itb.size
self.checker.mmu.dtb.size = self.mmu.dtb.size
self.checker.cpu_id = self.cpu_id
else:
print("ERROR: Checker only supported under ARM ISA!")
exit(1)
# Deprecated
DerivO3CPU = O3CPU
needsTSO = Param.Bool(False, "Enable TSO Memory model")

33
src/cpu/o3/BaseO3Checker.py Normal file
View File

@@ -0,0 +1,33 @@
# Copyright (c) 2007 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
from m5.params import *
from m5.objects.CheckerCPU import CheckerCPU
class BaseO3Checker(CheckerCPU):
type = 'BaseO3Checker'
cxx_class = 'gem5::o3::Checker'
cxx_header = 'cpu/o3/checker.hh'

6
src/cpu/o3/SConscript
View File

@@ -30,10 +30,10 @@ import sys
Import('*')
if 'O3CPU' in env['CPU_MODELS']:
if env['TARGET_ISA'] != 'null':
SimObject('FUPool.py', sim_objects=['FUPool'])
SimObject('FuncUnitConfig.py', sim_objects=[])
SimObject('O3CPU.py', sim_objects=['O3CPU'], enums=[
SimObject('BaseO3CPU.py', sim_objects=['BaseO3CPU'], enums=[
'SMTFetchPolicy', 'SMTQueuePolicy', 'CommitPolicy'])
Source('commit.cc')
@@ -74,5 +74,5 @@ if 'O3CPU' in env['CPU_MODELS']:
'IQ', 'ROB', 'FreeList', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit',
'DynInst', 'O3CPU', 'Activity', 'Scoreboard', 'Writeback' ])
SimObject('O3Checker.py', sim_objects=['O3Checker'])
SimObject('BaseO3Checker.py', sim_objects=['BaseO3Checker'])
Source('checker.cc')

4
src/cpu/o3/commit.cc
View File

@@ -64,7 +64,7 @@
#include "debug/ExecFaulting.hh"
#include "debug/HtmCpu.hh"
#include "debug/O3PipeView.hh"
#include "params/O3CPU.hh"
#include "params/BaseO3CPU.hh"
#include "sim/faults.hh"
#include "sim/full_system.hh"
@@ -82,7 +82,7 @@ Commit::processTrapEvent(ThreadID tid)
trapSquash[tid] = true;
}
Commit::Commit(CPU *_cpu, const O3CPUParams &params)
Commit::Commit(CPU *_cpu, const BaseO3CPUParams &params)
: commitPolicy(params.smtCommitPolicy),
cpu(_cpu),
iewToCommitDelay(params.iewToCommitDelay),

4
src/cpu/o3/commit.hh
View File

@@ -59,7 +59,7 @@
namespace gem5
{
struct O3CPUParams;
struct BaseO3CPUParams;
namespace o3
{
@@ -132,7 +132,7 @@ class Commit
public:
/** Construct a Commit with the given parameters. */
Commit(CPU *_cpu, const O3CPUParams &params);
Commit(CPU *_cpu, const BaseO3CPUParams &params);
/** Returns the name of the Commit. */
std::string name() const;

2
src/cpu/o3/cpu.cc
View File

@@ -70,7 +70,7 @@ struct BaseCPUParams;
namespace o3
{
CPU::CPU(const O3CPUParams &params)
CPU::CPU(const BaseO3CPUParams &params)
: BaseCPU(params),
mmu(params.mmu),
tickEvent([this]{ tick(); }, "O3CPU tick",

4
src/cpu/o3/cpu.hh
View File

@@ -68,7 +68,7 @@
#include "cpu/base.hh"
#include "cpu/simple_thread.hh"
#include "cpu/timebuf.hh"
#include "params/O3CPU.hh"
#include "params/BaseO3CPU.hh"
#include "sim/process.hh"
namespace gem5
@@ -169,7 +169,7 @@ class CPU : public BaseCPU
public:
/** Constructs a CPU with the given parameters. */
CPU(const O3CPUParams &params);
CPU(const BaseO3CPUParams &params);
ProbePointArg<PacketPtr> *ppInstAccessComplete;
ProbePointArg<std::pair<DynInstPtr, PacketPtr> > *ppDataAccessComplete;

4
src/cpu/o3/decode.cc
View File

@@ -49,7 +49,7 @@
#include "debug/Activity.hh"
#include "debug/Decode.hh"
#include "debug/O3PipeView.hh"
#include "params/O3CPU.hh"
#include "params/BaseO3CPU.hh"
#include "sim/full_system.hh"
// clang complains about std::set being overloaded with Packet::set if
@@ -62,7 +62,7 @@ namespace gem5
namespace o3
{
Decode::Decode(CPU *_cpu, const O3CPUParams &params)
Decode::Decode(CPU *_cpu, const BaseO3CPUParams &params)
: cpu(_cpu),
renameToDecodeDelay(params.renameToDecodeDelay),
iewToDecodeDelay(params.iewToDecodeDelay),

4
src/cpu/o3/decode.hh
View File

@@ -52,7 +52,7 @@
namespace gem5
{
struct O3CPUParams;
struct BaseO3CPUParams;
namespace o3
{
@@ -98,7 +98,7 @@ class Decode
public:
/** Decode constructor. */
Decode(CPU *_cpu, const O3CPUParams &params);
Decode(CPU *_cpu, const BaseO3CPUParams &params);
void startupStage();

4
src/cpu/o3/fetch.cc
View File

@@ -63,7 +63,7 @@
#include "debug/O3CPU.hh"
#include "debug/O3PipeView.hh"
#include "mem/packet.hh"
#include "params/O3CPU.hh"
#include "params/BaseO3CPU.hh"
#include "sim/byteswap.hh"
#include "sim/core.hh"
#include "sim/eventq.hh"
@@ -81,7 +81,7 @@ Fetch::IcachePort::IcachePort(Fetch *_fetch, CPU *_cpu) :
{}
Fetch::Fetch(CPU *_cpu, const O3CPUParams &params)
Fetch::Fetch(CPU *_cpu, const BaseO3CPUParams &params)
: fetchPolicy(params.smtFetchPolicy),
cpu(_cpu),
branchPred(nullptr),

4
src/cpu/o3/fetch.hh
View File

@@ -61,7 +61,7 @@
namespace gem5
{
struct O3CPUParams;
struct BaseO3CPUParams;
namespace o3
{
@@ -203,7 +203,7 @@ class Fetch
public:
/** Fetch constructor. */
Fetch(CPU *_cpu, const O3CPUParams &params);
Fetch(CPU *_cpu, const BaseO3CPUParams &params);
/** Returns the name of fetch. */
std::string name() const;

4
src/cpu/o3/iew.cc
View File

@@ -57,7 +57,7 @@
#include "debug/Drain.hh"
#include "debug/IEW.hh"
#include "debug/O3PipeView.hh"
#include "params/O3CPU.hh"
#include "params/BaseO3CPU.hh"
namespace gem5
{
@@ -65,7 +65,7 @@ namespace gem5
namespace o3
{
IEW::IEW(CPU *_cpu, const O3CPUParams &params)
IEW::IEW(CPU *_cpu, const BaseO3CPUParams &params)
: issueToExecQueue(params.backComSize, params.forwardComSize),
cpu(_cpu),
instQueue(_cpu, this, params),

4
src/cpu/o3/iew.hh
View File

@@ -58,7 +58,7 @@
namespace gem5
{
struct O3CPUParams;
struct BaseO3CPUParams;
namespace o3
{
@@ -127,7 +127,7 @@ class IEW
public:
/** Constructs a IEW with the given parameters. */
IEW(CPU *_cpu, const O3CPUParams &params);
IEW(CPU *_cpu, const BaseO3CPUParams &params);
/** Returns the name of the IEW stage. */
std::string name() const;

4
src/cpu/o3/inst_queue.cc
View File

@@ -50,7 +50,7 @@
#include "cpu/o3/limits.hh"
#include "debug/IQ.hh"
#include "enums/OpClass.hh"
#include "params/O3CPU.hh"
#include "params/BaseO3CPU.hh"
#include "sim/core.hh"
// clang complains about std::set being overloaded with Packet::set if
@@ -85,7 +85,7 @@ InstructionQueue::FUCompletion::description() const
}
InstructionQueue::InstructionQueue(CPU *cpu_ptr, IEW *iew_ptr,
const O3CPUParams &params)
const BaseO3CPUParams &params)
: cpu(cpu_ptr),
iewStage(iew_ptr),
fuPool(params.fuPool),

5
src/cpu/o3/inst_queue.hh
View File

@@ -64,7 +64,7 @@
namespace gem5
{
struct O3CPUParams;
struct BaseO3CPUParams;
namespace memory
{
@@ -130,7 +130,8 @@ class InstructionQueue
};
/** Constructs an IQ. */
InstructionQueue(CPU *cpu_ptr, IEW *iew_ptr, const O3CPUParams &params);
InstructionQueue(CPU *cpu_ptr, IEW *iew_ptr,
const BaseO3CPUParams &params);
/** Destructs the IQ. */
~InstructionQueue();

4
src/cpu/o3/lsq.cc
View File

@@ -56,7 +56,7 @@
#include "debug/HtmCpu.hh"
#include "debug/LSQ.hh"
#include "debug/Writeback.hh"
#include "params/O3CPU.hh"
#include "params/BaseO3CPU.hh"
namespace gem5
{
@@ -68,7 +68,7 @@ LSQ::DcachePort::DcachePort(LSQ *_lsq, CPU *_cpu) :
RequestPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq), cpu(_cpu)
{}
LSQ::LSQ(CPU *cpu_ptr, IEW *iew_ptr, const O3CPUParams &params)
LSQ::LSQ(CPU *cpu_ptr, IEW *iew_ptr, const BaseO3CPUParams &params)
: cpu(cpu_ptr), iewStage(iew_ptr),
_cacheBlocked(false),
cacheStorePorts(params.cacheStorePorts), usedStorePorts(0),

4
src/cpu/o3/lsq.hh
View File

@@ -63,7 +63,7 @@
namespace gem5
{
struct O3CPUParams;
struct BaseO3CPUParams;
namespace o3
{
@@ -647,7 +647,7 @@ class LSQ
};
/** Constructs an LSQ with the given parameters. */
LSQ(CPU *cpu_ptr, IEW *iew_ptr, const O3CPUParams &params);
LSQ(CPU *cpu_ptr, IEW *iew_ptr, const BaseO3CPUParams &params);
/** Returns the name of the LSQ. */
std::string name() const;

2
src/cpu/o3/lsq_unit.cc
View File

@@ -201,7 +201,7 @@ LSQUnit::LSQUnit(uint32_t lqEntries, uint32_t sqEntries)
}
void
LSQUnit::init(CPU *cpu_ptr, IEW *iew_ptr, const O3CPUParams &params,
LSQUnit::init(CPU *cpu_ptr, IEW *iew_ptr, const BaseO3CPUParams &params,
LSQ *lsq_ptr, unsigned id)
{
lsqID = id;

4
src/cpu/o3/lsq_unit.hh
View File

@@ -67,7 +67,7 @@
namespace gem5
{
struct O3CPUParams;
struct BaseO3CPUParams;
namespace o3
{
@@ -223,7 +223,7 @@ class LSQUnit
}
/** Initializes the LSQ unit with the specified number of entries. */
void init(CPU *cpu_ptr, IEW *iew_ptr, const O3CPUParams &params,
void init(CPU *cpu_ptr, IEW *iew_ptr, const BaseO3CPUParams &params,
LSQ *lsq_ptr, unsigned id);
/** Returns the name of the LSQ unit. */

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