c498d8bced
The BaseCPU type had been specializing itself based on the value of TARGET_ISA, which is not compatible with building more than one ISA at a time. This change refactors the CPU models so that the BaseCPU is more general, and the ISA specific components are added to the CPU when the CPU types are fully specialized. For instance, The AtomicSimpleCPU has a version called X86AtomicSimpleCPU which installs the X86 specific aspects of the CPU. This specialization is done in three ways. 1. The mmu parameter is assigned an instance of the architecture specific MMU type. This provides a reasonable default, but also avoids having having to use the ISA specific type when the parameter is created. 2. The ISA specific types are made available as class attributes, and the utility functions (including __init__!) in the BaseCPU class can refer to them to get the types they need to set up the CPU at run time. Because SimObjects have strange, unhelpful semantics as far as assigning to their attributes, these types need to be set up in a non-SimObject class, which is then brought in as a base of the actual SimObject type. Because the metaclass of this other type is just "type", things work like you would expect. The SimObject doesn't do any special processing of base classes if they aren't also SimObjects, so these attributes survive and are accessible using normal lookup in the BaseCPU class. 3. There are some methods like addCheckerCPU and properties like needsTSO which have ISA specific values or behaviors. These are set in the ISA specific subclass, where they are inherently specific to an ISA and don't need to check TARGET_ISA. Also, the DummyChecker which was set up for the BaseSimpleCPU which doesn't actually do anything in either C++ or python was not carried forward. The CPU type still exists, but it isn't installed in the simple CPUs. To provide backward compatibility, each ISA implements a .py file which matches the original .py for a CPU, and the original is renamed with a Base prefix. The ISA specific version creates an alias with the old CPU name which maps to the ISA specific type. This way, old scripts which refer to, for example, AtomicSimpleCPU, will get the X86AtomicSimpleCPU if the x86 version was compiled in, the ArmAtomicSimpleCPU on arm, etc. Unfortunately, because of how tags on PySource and by extension SimObjects are implemented right now, if you set the tags on two SimObjects or PySources which have the same module path, the later will overwrite the former whether or not they both would be included. There are some changes in review which would revamp this and make it work like you would expect, without this central bookkeeping which has the conflict. Since I can't use that here, I fell back to checking TARGET_ISA to decide whether to tell SCons about those files at all. In the long term, this mechanism should be revamped so that these compatibility types are only available if there is exactly one ISA compiled into gem5. After the configs have been updated and no longer assume they can use AtomicSimpleCPU in all cases, then these types can be deleted. Also, because ISAs can now either provide subclasses for a CPU or not, the CPU_MODELS variable has been removed, meaning the non-ISA specialized versions of those CPU models will always be included in gem5, except when building the NULL ISA. In the future, a more granular config mechanism will hopefully be implemented for *all* of gem5 and not just the CPUs, and these can be conditional again in case you only need certain models, and want to reduce build time or binary size by excluding the others. Change-Id: I02fc3f645c551678ede46268bbea9f66c3f6c74b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52490 Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com> Maintainer: Gabe Black <gabe.black@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>
90 lines
4.1 KiB
Python
90 lines
4.1 KiB
Python
# -*- mode:python -*-
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# Copyright (c) 2013 ARM Limited
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# Copyright (c) 2014 Sven Karlsson
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# Copyright (c) 2020 Barkhausen Institut
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# Copyright (c) 2021 Huawei International
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# All rights reserved
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#
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# The license below extends only to copyright in the software and shall
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# not be construed as granting a license to any other intellectual
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# property including but not limited to intellectual property relating
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# to a hardware implementation of the functionality of the software
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# licensed hereunder. You may use the software subject to the license
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# terms below provided that you ensure that this notice is replicated
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# unmodified and in its entirety in all distributions of the software,
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# modified or unmodified, in source code or in binary form.
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#
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# Copyright (c) 2016 The University of Virginia
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# All rights reserved.
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#
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# Redistribution and use in source and binary forms, with or without
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# modification, are permitted provided that the following conditions are
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# met: redistributions of source code must retain the above copyright
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# notice, this list of conditions and the following disclaimer;
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# redistributions in binary form must reproduce the above copyright
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# notice, this list of conditions and the following disclaimer in the
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# documentation and/or other materials provided with the distribution;
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# neither the name of the copyright holders nor the names of its
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# contributors may be used to endorse or promote products derived from
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# this software without specific prior written permission.
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#
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# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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Import('*')
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Source('decoder.cc', tags='riscv isa')
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Source('faults.cc', tags='riscv isa')
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Source('isa.cc', tags='riscv isa')
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Source('process.cc', tags='riscv isa')
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Source('pagetable.cc', tags='riscv isa')
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Source('pagetable_walker.cc', tags='riscv isa')
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Source('pma_checker.cc', tags='riscv isa')
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Source('pmp.cc', tags='riscv isa')
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Source('reg_abi.cc', tags='riscv isa')
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Source('remote_gdb.cc', tags='riscv isa')
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Source('tlb.cc', tags='riscv isa')
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Source('linux/se_workload.cc', tags='riscv isa')
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Source('linux/fs_workload.cc', tags='riscv isa')
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Source('bare_metal/fs_workload.cc', tags='riscv isa')
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SimObject('PMAChecker.py', sim_objects=['PMAChecker'], tags='riscv isa')
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SimObject('PMP.py', sim_objects=['PMP'], tags='riscv isa')
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SimObject('RiscvDecoder.py', sim_objects=['RiscvDecoder'], tags='riscv isa')
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SimObject('RiscvFsWorkload.py', sim_objects=['RiscvBareMetal', 'RiscvLinux'],
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tags='riscv isa')
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SimObject('RiscvInterrupts.py', sim_objects=['RiscvInterrupts'],
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tags='riscv isa')
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SimObject('RiscvISA.py', sim_objects=['RiscvISA'], tags='riscv isa')
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SimObject('RiscvMMU.py', sim_objects=['RiscvMMU'], tags='riscv isa')
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SimObject('RiscvSeWorkload.py', sim_objects=[
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'RiscvSEWorkload', 'RiscvEmuLinux'], tags='riscv isa')
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SimObject('RiscvTLB.py', sim_objects=['RiscvPagetableWalker', 'RiscvTLB'],
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tags='riscv isa')
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SimObject('RiscvCPU.py', sim_objects=[], tags='riscv isa')
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if env['TARGET_ISA'] == 'riscv':
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SimObject('AtomicSimpleCPU.py', sim_objects=[], tags='riscv isa')
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SimObject('TimingSimpleCPU.py', sim_objects=[], tags='riscv isa')
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SimObject('NonCachingSimpleCPU.py', sim_objects=[], tags='riscv isa')
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SimObject('O3CPU.py', sim_objects=[], tags='riscv isa')
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SimObject('MinorCPU.py', sim_objects=[], tags='riscv isa')
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DebugFlag('RiscvMisc', tags='riscv isa')
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DebugFlag('PMP', tags='riscv isa')
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# Add in files generated by the ISA description.
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ISADesc('isa/main.isa', tags='riscv isa')
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