From c498d8bced61bae51345a352b199b5c75eabadf8 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Fri, 29 Oct 2021 18:40:54 -0700 Subject: [PATCH] cpu: Specialize CPUs for an ISA at the leaves, not BaseCPU. The BaseCPU type had been specializing itself based on the value of TARGET_ISA, which is not compatible with building more than one ISA at a time. This change refactors the CPU models so that the BaseCPU is more general, and the ISA specific components are added to the CPU when the CPU types are fully specialized. For instance, The AtomicSimpleCPU has a version called X86AtomicSimpleCPU which installs the X86 specific aspects of the CPU. This specialization is done in three ways. 1. The mmu parameter is assigned an instance of the architecture specific MMU type. This provides a reasonable default, but also avoids having having to use the ISA specific type when the parameter is created. 2. The ISA specific types are made available as class attributes, and the utility functions (including __init__!) in the BaseCPU class can refer to them to get the types they need to set up the CPU at run time. Because SimObjects have strange, unhelpful semantics as far as assigning to their attributes, these types need to be set up in a non-SimObject class, which is then brought in as a base of the actual SimObject type. Because the metaclass of this other type is just "type", things work like you would expect. The SimObject doesn't do any special processing of base classes if they aren't also SimObjects, so these attributes survive and are accessible using normal lookup in the BaseCPU class. 3. There are some methods like addCheckerCPU and properties like needsTSO which have ISA specific values or behaviors. These are set in the ISA specific subclass, where they are inherently specific to an ISA and don't need to check TARGET_ISA. Also, the DummyChecker which was set up for the BaseSimpleCPU which doesn't actually do anything in either C++ or python was not carried forward. The CPU type still exists, but it isn't installed in the simple CPUs. To provide backward compatibility, each ISA implements a .py file which matches the original .py for a CPU, and the original is renamed with a Base prefix. The ISA specific version creates an alias with the old CPU name which maps to the ISA specific type. This way, old scripts which refer to, for example, AtomicSimpleCPU, will get the X86AtomicSimpleCPU if the x86 version was compiled in, the ArmAtomicSimpleCPU on arm, etc. Unfortunately, because of how tags on PySource and by extension SimObjects are implemented right now, if you set the tags on two SimObjects or PySources which have the same module path, the later will overwrite the former whether or not they both would be included. There are some changes in review which would revamp this and make it work like you would expect, without this central bookkeeping which has the conflict. Since I can't use that here, I fell back to checking TARGET_ISA to decide whether to tell SCons about those files at all. In the long term, this mechanism should be revamped so that these compatibility types are only available if there is exactly one ISA compiled into gem5. After the configs have been updated and no longer assume they can use AtomicSimpleCPU in all cases, then these types can be deleted. Also, because ISAs can now either provide subclasses for a CPU or not, the CPU_MODELS variable has been removed, meaning the non-ISA specialized versions of those CPU models will always be included in gem5, except when building the NULL ISA. In the future, a more granular config mechanism will hopefully be implemented for *all* of gem5 and not just the CPUs, and these can be conditional again in case you only need certain models, and want to reduce build time or binary size by excluding the others. Change-Id: I02fc3f645c551678ede46268bbea9f66c3f6c74b Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52490 Reviewed-by: Andreas Sandberg Maintainer: Gabe Black Tested-by: kokoro --- build_opts/ARM | 1 - build_opts/ARM_MESI_Three_Level | 1 - build_opts/ARM_MESI_Three_Level_HTM | 1 - build_opts/ARM_MOESI_hammer | 1 - build_opts/GCN3_X86 | 1 - build_opts/Garnet_standalone | 1 - build_opts/MIPS | 1 - build_opts/NULL | 1 - build_opts/NULL_MESI_Two_Level | 1 - build_opts/NULL_MOESI_CMP_directory | 1 - build_opts/NULL_MOESI_CMP_token | 1 - build_opts/NULL_MOESI_hammer | 1 - build_opts/POWER | 1 - build_opts/RISCV | 1 - build_opts/SPARC | 1 - build_opts/VEGA_X86 | 1 - build_opts/X86 | 3 +- build_opts/X86_MESI_Two_Level | 1 - build_opts/X86_MI_example | 1 - build_opts/X86_MOESI_AMD_Base | 1 - configs/common/cores/arm/HPI.py | 2 +- configs/common/cores/arm/O3_ARM_v7a.py | 2 +- configs/common/cores/arm/ex5_LITTLE.py | 2 +- configs/common/cores/arm/ex5_big.py | 2 +- src/arch/arm/ArmCPU.py | 78 +++++++++++++++++++ src/arch/arm/AtomicSimpleCPU.py | 28 +++++++ src/arch/arm/MinorCPU.py | 28 +++++++ src/arch/arm/NonCachingSimpleCPU.py | 28 +++++++ src/{cpu/o3/SConsopts => arch/arm/O3CPU.py} | 12 +-- src/{cpu/o3 => arch/arm}/O3Checker.py | 11 +-- src/arch/arm/SConscript | 9 +++ src/arch/arm/TimingSimpleCPU.py | 28 +++++++ src/arch/arm/fastmodel/iris/Iris.py | 10 ++- src/arch/arm/kvm/BaseArmKvmCPU.py | 6 +- src/arch/mips/AtomicSimpleCPU.py | 28 +++++++ .../minor/SConsopts => arch/mips/MipsCPU.py} | 41 ++++++---- src/arch/mips/NonCachingSimpleCPU.py | 28 +++++++ .../checker/SConsopts => arch/mips/O3CPU.py} | 12 +-- src/arch/mips/SConscript | 7 ++ src/arch/mips/TimingSimpleCPU.py | 28 +++++++ src/arch/power/AtomicSimpleCPU.py | 28 +++++++ src/arch/power/NonCachingSimpleCPU.py | 28 +++++++ .../simple/SConsopts => arch/power/O3CPU.py} | 12 +-- src/arch/power/PowerCPU.py | 51 ++++++++++++ src/arch/power/SConscript | 7 ++ src/arch/power/TimingSimpleCPU.py | 28 +++++++ src/arch/riscv/AtomicSimpleCPU.py | 28 +++++++ src/arch/riscv/MinorCPU.py | 28 +++++++ src/arch/riscv/NonCachingSimpleCPU.py | 28 +++++++ src/{cpu/SConsopts => arch/riscv/O3CPU.py} | 12 +-- src/arch/riscv/RiscvCPU.py | 55 +++++++++++++ src/arch/riscv/SConscript | 8 ++ src/arch/riscv/TimingSimpleCPU.py | 28 +++++++ src/arch/sparc/AtomicSimpleCPU.py | 28 +++++++ src/arch/sparc/NonCachingSimpleCPU.py | 28 +++++++ src/arch/sparc/O3CPU.py | 31 ++++++++ src/arch/sparc/SConscript | 7 ++ src/arch/sparc/SparcCPU.py | 51 ++++++++++++ src/arch/sparc/TimingSimpleCPU.py | 28 +++++++ src/arch/x86/AtomicSimpleCPU.py | 28 +++++++ src/arch/x86/NonCachingSimpleCPU.py | 28 +++++++ src/arch/x86/O3CPU.py | 31 ++++++++ src/arch/x86/SConscript | 7 ++ src/arch/x86/TimingSimpleCPU.py | 28 +++++++ src/arch/x86/X86CPU.py | 62 +++++++++++++++ src/arch/x86/kvm/X86KvmCPU.py | 6 +- src/cpu/BaseCPU.py | 56 +++---------- .../minor/{MinorCPU.py => BaseMinorCPU.py} | 4 +- src/cpu/minor/SConscript | 6 +- src/cpu/minor/cpu.cc | 2 +- src/cpu/minor/cpu.hh | 4 +- src/cpu/minor/decode.cc | 2 +- src/cpu/minor/decode.hh | 2 +- src/cpu/minor/execute.cc | 2 +- src/cpu/minor/execute.hh | 2 +- src/cpu/minor/fetch1.cc | 2 +- src/cpu/minor/fetch1.hh | 2 +- src/cpu/minor/fetch2.cc | 2 +- src/cpu/minor/fetch2.hh | 4 +- src/cpu/minor/pipeline.cc | 2 +- src/cpu/minor/pipeline.hh | 4 +- src/cpu/o3/{O3CPU.py => BaseO3CPU.py} | 61 +++++---------- src/cpu/o3/BaseO3Checker.py | 33 ++++++++ src/cpu/o3/SConscript | 6 +- src/cpu/o3/commit.cc | 4 +- src/cpu/o3/commit.hh | 4 +- src/cpu/o3/cpu.cc | 2 +- src/cpu/o3/cpu.hh | 4 +- src/cpu/o3/decode.cc | 4 +- src/cpu/o3/decode.hh | 4 +- src/cpu/o3/fetch.cc | 4 +- src/cpu/o3/fetch.hh | 4 +- src/cpu/o3/iew.cc | 4 +- src/cpu/o3/iew.hh | 4 +- src/cpu/o3/inst_queue.cc | 4 +- src/cpu/o3/inst_queue.hh | 5 +- src/cpu/o3/lsq.cc | 4 +- src/cpu/o3/lsq.hh | 4 +- src/cpu/o3/lsq_unit.cc | 2 +- src/cpu/o3/lsq_unit.hh | 4 +- src/cpu/o3/mem_dep_unit.cc | 6 +- src/cpu/o3/mem_dep_unit.hh | 6 +- src/cpu/o3/probe/SConscript | 2 +- src/cpu/o3/rename.cc | 4 +- src/cpu/o3/rename.hh | 4 +- src/cpu/o3/rob.cc | 4 +- src/cpu/o3/rob.hh | 4 +- ...micSimpleCPU.py => BaseAtomicSimpleCPU.py} | 4 +- ...impleCPU.py => BaseNonCachingSimpleCPU.py} | 6 +- src/cpu/simple/BaseSimpleCPU.py | 12 --- ...ingSimpleCPU.py => BaseTimingSimpleCPU.py} | 4 +- src/cpu/simple/SConscript | 16 ++-- src/cpu/simple/atomic.cc | 4 +- src/cpu/simple/atomic.hh | 4 +- src/cpu/simple/noncaching.cc | 3 +- src/cpu/simple/noncaching.hh | 4 +- src/cpu/simple/probes/SConscript | 2 +- src/cpu/simple/timing.cc | 4 +- src/cpu/simple/timing.hh | 4 +- src/cpu/testers/memtest/SConscript | 1 - 120 files changed, 1194 insertions(+), 277 deletions(-) create mode 100644 src/arch/arm/ArmCPU.py create mode 100644 src/arch/arm/AtomicSimpleCPU.py create mode 100644 src/arch/arm/MinorCPU.py create mode 100644 src/arch/arm/NonCachingSimpleCPU.py rename src/{cpu/o3/SConsopts => arch/arm/O3CPU.py} (90%) rename src/{cpu/o3 => arch/arm}/O3Checker.py (83%) create mode 100644 src/arch/arm/TimingSimpleCPU.py create mode 100644 src/arch/mips/AtomicSimpleCPU.py rename src/{cpu/minor/SConsopts => arch/mips/MipsCPU.py} (62%) create mode 100644 src/arch/mips/NonCachingSimpleCPU.py rename src/{cpu/checker/SConsopts => arch/mips/O3CPU.py} (89%) create mode 100644 src/arch/mips/TimingSimpleCPU.py create mode 100644 src/arch/power/AtomicSimpleCPU.py create mode 100644 src/arch/power/NonCachingSimpleCPU.py rename src/{cpu/simple/SConsopts => arch/power/O3CPU.py} (88%) create mode 100644 src/arch/power/PowerCPU.py create mode 100644 src/arch/power/TimingSimpleCPU.py create mode 100644 src/arch/riscv/AtomicSimpleCPU.py create mode 100644 src/arch/riscv/MinorCPU.py create mode 100644 src/arch/riscv/NonCachingSimpleCPU.py rename src/{cpu/SConsopts => arch/riscv/O3CPU.py} (86%) create mode 100644 src/arch/riscv/RiscvCPU.py create mode 100644 src/arch/riscv/TimingSimpleCPU.py create mode 100644 src/arch/sparc/AtomicSimpleCPU.py create mode 100644 src/arch/sparc/NonCachingSimpleCPU.py create mode 100644 src/arch/sparc/O3CPU.py create mode 100644 src/arch/sparc/SparcCPU.py create mode 100644 src/arch/sparc/TimingSimpleCPU.py create mode 100644 src/arch/x86/AtomicSimpleCPU.py create mode 100644 src/arch/x86/NonCachingSimpleCPU.py create mode 100644 src/arch/x86/O3CPU.py create mode 100644 src/arch/x86/TimingSimpleCPU.py create mode 100644 src/arch/x86/X86CPU.py rename src/cpu/minor/{MinorCPU.py => BaseMinorCPU.py} (99%) rename src/cpu/o3/{O3CPU.py => BaseO3CPU.py} (78%) create mode 100644 src/cpu/o3/BaseO3Checker.py rename src/cpu/simple/{AtomicSimpleCPU.py => BaseAtomicSimpleCPU.py} (97%) rename src/cpu/simple/{NonCachingSimpleCPU.py => BaseNonCachingSimpleCPU.py} (94%) rename src/cpu/simple/{TimingSimpleCPU.py => BaseTimingSimpleCPU.py} (96%) diff --git a/build_opts/ARM b/build_opts/ARM index e4cb9a5066..5b7da10e22 100644 --- a/build_opts/ARM +++ b/build_opts/ARM @@ -1,3 +1,2 @@ TARGET_ISA = 'arm' -CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU,MinorCPU' PROTOCOL = 'CHI' diff --git a/build_opts/ARM_MESI_Three_Level b/build_opts/ARM_MESI_Three_Level index 29a429ce68..2ca31b64cc 100644 --- a/build_opts/ARM_MESI_Three_Level +++ b/build_opts/ARM_MESI_Three_Level @@ -2,5 +2,4 @@ # All rights reserved. TARGET_ISA = 'arm' -CPU_MODELS = 'TimingSimpleCPU,O3CPU' PROTOCOL = 'MESI_Three_Level' diff --git a/build_opts/ARM_MESI_Three_Level_HTM b/build_opts/ARM_MESI_Three_Level_HTM index fd7c164940..703398d786 100644 --- a/build_opts/ARM_MESI_Three_Level_HTM +++ b/build_opts/ARM_MESI_Three_Level_HTM @@ -2,5 +2,4 @@ # All rights reserved. TARGET_ISA = 'arm' -CPU_MODELS = 'TimingSimpleCPU,O3CPU' PROTOCOL = 'MESI_Three_Level_HTM' diff --git a/build_opts/ARM_MOESI_hammer b/build_opts/ARM_MOESI_hammer index 2ba8ce835b..bd5c63f0d2 100644 --- a/build_opts/ARM_MOESI_hammer +++ b/build_opts/ARM_MOESI_hammer @@ -2,5 +2,4 @@ # All rights reserved. TARGET_ISA = 'arm' -CPU_MODELS = 'TimingSimpleCPU,O3CPU' PROTOCOL = 'MOESI_hammer' diff --git a/build_opts/GCN3_X86 b/build_opts/GCN3_X86 index 21e3cf0e45..b39690812e 100644 --- a/build_opts/GCN3_X86 +++ b/build_opts/GCN3_X86 @@ -2,4 +2,3 @@ PROTOCOL = 'GPU_VIPER' TARGET_ISA = 'x86' TARGET_GPU_ISA = 'gcn3' BUILD_GPU = True -CPU_MODELS = 'AtomicSimpleCPU,O3CPU,TimingSimpleCPU' diff --git a/build_opts/Garnet_standalone b/build_opts/Garnet_standalone index f749d54ca2..fd730c3f48 100644 --- a/build_opts/Garnet_standalone +++ b/build_opts/Garnet_standalone @@ -1,3 +1,2 @@ TARGET_ISA = 'null' -CPU_MODELS = '' PROTOCOL = 'Garnet_standalone' diff --git a/build_opts/MIPS b/build_opts/MIPS index ecb2b09725..26cb23c393 100644 --- a/build_opts/MIPS +++ b/build_opts/MIPS @@ -1,3 +1,2 @@ TARGET_ISA = 'mips' -CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU' PROTOCOL = 'MI_example' diff --git a/build_opts/NULL b/build_opts/NULL index 1242fa9ef6..b749729fbe 100644 --- a/build_opts/NULL +++ b/build_opts/NULL @@ -1,3 +1,2 @@ TARGET_ISA = 'null' -CPU_MODELS = '' PROTOCOL='MI_example' diff --git a/build_opts/NULL_MESI_Two_Level b/build_opts/NULL_MESI_Two_Level index db05046b52..09147b2250 100644 --- a/build_opts/NULL_MESI_Two_Level +++ b/build_opts/NULL_MESI_Two_Level @@ -1,3 +1,2 @@ TARGET_ISA = 'null' -CPU_MODELS = '' PROTOCOL = 'MESI_Two_Level' diff --git a/build_opts/NULL_MOESI_CMP_directory b/build_opts/NULL_MOESI_CMP_directory index 7136d0b93c..466a268c9d 100644 --- a/build_opts/NULL_MOESI_CMP_directory +++ b/build_opts/NULL_MOESI_CMP_directory @@ -1,3 +1,2 @@ TARGET_ISA = 'null' -CPU_MODELS = '' PROTOCOL='MOESI_CMP_directory' diff --git a/build_opts/NULL_MOESI_CMP_token b/build_opts/NULL_MOESI_CMP_token index 42fff75f36..0cd030503d 100644 --- a/build_opts/NULL_MOESI_CMP_token +++ b/build_opts/NULL_MOESI_CMP_token @@ -1,3 +1,2 @@ TARGET_ISA = 'null' -CPU_MODELS = '' PROTOCOL='MOESI_CMP_token' diff --git a/build_opts/NULL_MOESI_hammer b/build_opts/NULL_MOESI_hammer index ff4c22c4b2..39ebcae641 100644 --- a/build_opts/NULL_MOESI_hammer +++ b/build_opts/NULL_MOESI_hammer @@ -1,3 +1,2 @@ TARGET_ISA = 'null' -CPU_MODELS = '' PROTOCOL='MOESI_hammer' diff --git a/build_opts/POWER b/build_opts/POWER index 672046ceeb..35772a4795 100644 --- a/build_opts/POWER +++ b/build_opts/POWER @@ -1,3 +1,2 @@ TARGET_ISA = 'power' -CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU' PROTOCOL = 'MI_example' diff --git a/build_opts/RISCV b/build_opts/RISCV index 38abd92165..0bd069d489 100644 --- a/build_opts/RISCV +++ b/build_opts/RISCV @@ -1,3 +1,2 @@ TARGET_ISA = 'riscv' -CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,MinorCPU,O3CPU' PROTOCOL = 'MI_example' diff --git a/build_opts/SPARC b/build_opts/SPARC index 63ec7cbaff..98acfe2406 100644 --- a/build_opts/SPARC +++ b/build_opts/SPARC @@ -1,3 +1,2 @@ TARGET_ISA = 'sparc' -CPU_MODELS = 'AtomicSimpleCPU,TimingSimpleCPU,O3CPU' PROTOCOL = 'MI_example' diff --git a/build_opts/VEGA_X86 b/build_opts/VEGA_X86 index 796b556129..11e8232129 100644 --- a/build_opts/VEGA_X86 +++ b/build_opts/VEGA_X86 @@ -2,4 +2,3 @@ PROTOCOL = 'GPU_VIPER' TARGET_ISA = 'x86' TARGET_GPU_ISA = 'vega' BUILD_GPU = True -CPU_MODELS = 'AtomicSimpleCPU,O3CPU,TimingSimpleCPU' diff --git a/build_opts/X86 b/build_opts/X86 index 27c1b586b0..72b200acaa 100644 --- a/build_opts/X86 +++ b/build_opts/X86 @@ -1,4 +1,3 @@ TARGET_ISA = 'x86' -CPU_MODELS = 'TimingSimpleCPU,O3CPU,AtomicSimpleCPU' PROTOCOL = 'MESI_Two_Level' -NUMBER_BITS_PER_SET = '128' \ No newline at end of file +NUMBER_BITS_PER_SET = '128' diff --git a/build_opts/X86_MESI_Two_Level b/build_opts/X86_MESI_Two_Level index eba850b331..72b200acaa 100644 --- a/build_opts/X86_MESI_Two_Level +++ b/build_opts/X86_MESI_Two_Level @@ -1,4 +1,3 @@ TARGET_ISA = 'x86' -CPU_MODELS = 'TimingSimpleCPU,O3CPU,AtomicSimpleCPU' PROTOCOL = 'MESI_Two_Level' NUMBER_BITS_PER_SET = '128' diff --git a/build_opts/X86_MI_example b/build_opts/X86_MI_example index 60d1645c95..483cf0486a 100644 --- a/build_opts/X86_MI_example +++ b/build_opts/X86_MI_example @@ -1,3 +1,2 @@ TARGET_ISA = 'x86' -CPU_MODELS = 'TimingSimpleCPU,O3CPU,AtomicSimpleCPU' PROTOCOL = 'MI_example' diff --git a/build_opts/X86_MOESI_AMD_Base b/build_opts/X86_MOESI_AMD_Base index e85f36d822..261bedb925 100644 --- a/build_opts/X86_MOESI_AMD_Base +++ b/build_opts/X86_MOESI_AMD_Base @@ -1,3 +1,2 @@ PROTOCOL = 'MOESI_AMD_Base' TARGET_ISA = 'x86' -CPU_MODELS = 'AtomicSimpleCPU,O3CPU,TimingSimpleCPU' \ No newline at end of file diff --git a/configs/common/cores/arm/HPI.py b/configs/common/cores/arm/HPI.py index 620c01ebd5..3a11133a5b 100644 --- a/configs/common/cores/arm/HPI.py +++ b/configs/common/cores/arm/HPI.py @@ -1379,7 +1379,7 @@ class HPI_L2(Cache): write_buffers = 16 # prefetcher FIXME -class HPI(MinorCPU): +class HPI(ArmMinorCPU): # Inherit the doc string from the module to avoid repeating it # here. __doc__ = __doc__ diff --git a/configs/common/cores/arm/O3_ARM_v7a.py b/configs/common/cores/arm/O3_ARM_v7a.py index 8cacc65ebb..d032a1aa88 100644 --- a/configs/common/cores/arm/O3_ARM_v7a.py +++ b/configs/common/cores/arm/O3_ARM_v7a.py @@ -99,7 +99,7 @@ class O3_ARM_v7a_BP(BiModeBP): RASSize = 16 instShiftAmt = 2 -class O3_ARM_v7a_3(DerivO3CPU): +class O3_ARM_v7a_3(ArmO3CPU): LQEntries = 16 SQEntries = 16 LSQDepCheckShift = 0 diff --git a/configs/common/cores/arm/ex5_LITTLE.py b/configs/common/cores/arm/ex5_LITTLE.py index bcbaa922cd..57f6a6b812 100644 --- a/configs/common/cores/arm/ex5_LITTLE.py +++ b/configs/common/cores/arm/ex5_LITTLE.py @@ -88,7 +88,7 @@ class ex5_LITTLE_FUP(MinorFUPool): ex5_LITTLE_FP(), ex5_LITTLE_MemFU(), ex5_LITTLE_MiscFU()] -class ex5_LITTLE(MinorCPU): +class ex5_LITTLE(ArmMinorCPU): executeFuncUnits = ex5_LITTLE_FUP() class L1Cache(Cache): diff --git a/configs/common/cores/arm/ex5_big.py b/configs/common/cores/arm/ex5_big.py index eb5f53ff0c..de7a45063a 100644 --- a/configs/common/cores/arm/ex5_big.py +++ b/configs/common/cores/arm/ex5_big.py @@ -99,7 +99,7 @@ class ex5_big_BP(BiModeBP): RASSize = 48 instShiftAmt = 2 -class ex5_big(DerivO3CPU): +class ex5_big(ArmO3CPU): LQEntries = 16 SQEntries = 16 LSQDepCheckShift = 0 diff --git a/src/arch/arm/ArmCPU.py b/src/arch/arm/ArmCPU.py new file mode 100644 index 0000000000..c55d99bf1a --- /dev/null +++ b/src/arch/arm/ArmCPU.py @@ -0,0 +1,78 @@ +# Copyright 2021 Google, Inc. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.proxy import Self + +from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU +from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU +from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU +from m5.objects.BaseO3CPU import BaseO3CPU +from m5.objects.BaseO3Checker import BaseO3Checker +from m5.objects.BaseMinorCPU import BaseMinorCPU +from m5.objects.ArmDecoder import ArmDecoder +from m5.objects.ArmMMU import ArmMMU +from m5.objects.ArmInterrupts import ArmInterrupts +from m5.objects.ArmISA import ArmISA + +class ArmCPU: + ArchDecoder = ArmDecoder + ArchMMU = ArmMMU + ArchInterrupts = ArmInterrupts + ArchISA = ArmISA + +class ArmAtomicSimpleCPU(BaseAtomicSimpleCPU, ArmCPU): + mmu = ArmMMU() + +class ArmNonCachingSimpleCPU(BaseNonCachingSimpleCPU, ArmCPU): + mmu = ArmMMU() + +class ArmTimingSimpleCPU(BaseTimingSimpleCPU, ArmCPU): + mmu = ArmMMU() + +class ArmO3Checker(BaseO3Checker, ArmCPU): + mmu = ArmMMU() + +class ArmO3CPU(BaseO3CPU, ArmCPU): + mmu = ArmMMU() + + # For x86, each CC reg is used to hold only a subset of the + # flags, so we need 4-5 times the number of CC regs as + # physical integer regs to be sure we don't run out. In + # typical real machines, CC regs are not explicitly renamed + # (it's a side effect of int reg renaming), so they should + # never be the bottleneck here. + numPhysCCRegs = Self.numPhysIntRegs * 5 + + def addCheckerCpu(self): + self.checker = ArmO3Checker(workload=self.workload, + exitOnError=False, + updateOnError=True, + warnOnlyOnLoadError=True) + self.checker.mmu.itb.size = self.mmu.itb.size + self.checker.mmu.dtb.size = self.mmu.dtb.size + self.checker.cpu_id = self.cpu_id + +class ArmMinorCPU(BaseMinorCPU, ArmCPU): + mmu = ArmMMU() diff --git a/src/arch/arm/AtomicSimpleCPU.py b/src/arch/arm/AtomicSimpleCPU.py new file mode 100644 index 0000000000..c3a25ba52e --- /dev/null +++ b/src/arch/arm/AtomicSimpleCPU.py @@ -0,0 +1,28 @@ +# Copyright 2021 Google, Inc. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.objects.ArmCPU import ArmAtomicSimpleCPU + +AtomicSimpleCPU = ArmAtomicSimpleCPU diff --git a/src/arch/arm/MinorCPU.py b/src/arch/arm/MinorCPU.py new file mode 100644 index 0000000000..bac019774e --- /dev/null +++ b/src/arch/arm/MinorCPU.py @@ -0,0 +1,28 @@ +# Copyright 2021 Google, Inc. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.objects.ArmCPU import ArmMinorCPU + +MinorCPU = ArmMinorCPU diff --git a/src/arch/arm/NonCachingSimpleCPU.py b/src/arch/arm/NonCachingSimpleCPU.py new file mode 100644 index 0000000000..bfad3ba88b --- /dev/null +++ b/src/arch/arm/NonCachingSimpleCPU.py @@ -0,0 +1,28 @@ +# Copyright 2021 Google, Inc. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.objects.ArmCPU import ArmNonCachingSimpleCPU + +NonCachingSimpleCPU = ArmNonCachingSimpleCPU diff --git a/src/cpu/o3/SConsopts b/src/arch/arm/O3CPU.py similarity index 90% rename from src/cpu/o3/SConsopts rename to src/arch/arm/O3CPU.py index 3479484f16..54782e746e 100644 --- a/src/cpu/o3/SConsopts +++ b/src/arch/arm/O3CPU.py @@ -1,7 +1,4 @@ -# -*- mode:python -*- - -# Copyright (c) 2006 The Regents of The University of Michigan -# All rights reserved. +# Copyright 2021 Google, Inc. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are @@ -26,6 +23,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -Import('*') +from m5.objects.ArmCPU import ArmO3CPU -main.Append(ALL_CPU_MODELS=['O3CPU']) +O3CPU = ArmO3CPU + +# Deprecated +DerivO3CPU = O3CPU diff --git a/src/cpu/o3/O3Checker.py b/src/arch/arm/O3Checker.py similarity index 83% rename from src/cpu/o3/O3Checker.py rename to src/arch/arm/O3Checker.py index c343cd678e..0ac7ab42a7 100644 --- a/src/cpu/o3/O3Checker.py +++ b/src/arch/arm/O3Checker.py @@ -1,5 +1,4 @@ -# Copyright (c) 2007 The Regents of The University of Michigan -# All rights reserved. +# Copyright 2021 Google, Inc. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are @@ -24,10 +23,6 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -from m5.params import * -from m5.objects.CheckerCPU import CheckerCPU +from m5.objects.ArmCPU import ArmO3Checker -class O3Checker(CheckerCPU): - type = 'O3Checker' - cxx_class = 'gem5::o3::Checker' - cxx_header = 'cpu/o3/checker.hh' +O3Checker = ArmO3Checker diff --git a/src/arch/arm/SConscript b/src/arch/arm/SConscript index b13821270e..a00ba8d749 100644 --- a/src/arch/arm/SConscript +++ b/src/arch/arm/SConscript @@ -112,6 +112,15 @@ SimObject('ArmTLB.py', sim_objects=['ArmTLB'], enums=['ArmLookupLevel'], tags='arm isa') SimObject('ArmPMU.py', sim_objects=['ArmPMU'], tags='arm isa') +SimObject('ArmCPU.py', sim_objects=[], tags='arm isa') +if env['TARGET_ISA'] == 'arm': + SimObject('AtomicSimpleCPU.py', sim_objects=[], tags='arm isa') + SimObject('TimingSimpleCPU.py', sim_objects=[], tags='arm isa') + SimObject('NonCachingSimpleCPU.py', sim_objects=[], tags='arm isa') + SimObject('O3CPU.py', sim_objects=[], tags='arm isa') + SimObject('O3Checker.py', sim_objects=[], tags='arm isa') + SimObject('MinorCPU.py', sim_objects=[], tags='arm isa') + DebugFlag('Arm', tags='arm isa') DebugFlag('ArmTme', 'Transactional Memory Extension', tags='arm isa') DebugFlag('Semihosting', tags='arm isa') diff --git a/src/arch/arm/TimingSimpleCPU.py b/src/arch/arm/TimingSimpleCPU.py new file mode 100644 index 0000000000..8a20a36345 --- /dev/null +++ b/src/arch/arm/TimingSimpleCPU.py @@ -0,0 +1,28 @@ +# Copyright 2021 Google, Inc. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.objects.ArmCPU import ArmTimingSimpleCPU + +TimingSimpleCPU = ArmTimingSimpleCPU diff --git a/src/arch/arm/fastmodel/iris/Iris.py b/src/arch/arm/fastmodel/iris/Iris.py index 497971531c..51eb3943dc 100644 --- a/src/arch/arm/fastmodel/iris/Iris.py +++ b/src/arch/arm/fastmodel/iris/Iris.py @@ -66,7 +66,12 @@ class IrisISA(BaseISA): cxx_class = 'gem5::Iris::ISA' cxx_header = 'arch/arm/fastmodel/iris/isa.hh' -class IrisBaseCPU(BaseCPU): +class IrisCPU(): + ArchMMU = IrisMMU + ArchInterrupts = IrisInterrupts + ArchISA = IrisISA + +class IrisBaseCPU(BaseCPU, IrisCPU): type = 'IrisBaseCPU' abstract = True cxx_class = 'gem5::Iris::BaseCPU' @@ -97,6 +102,3 @@ class IrisBaseCPU(BaseCPU): self.isa = [ IrisISA() for i in range(self.numThreads) ] else: assert(len(self.isa) == int(self.numThreads)) - - def createInterruptController(self): - self.interrupts = [ IrisInterrupts() for i in range(self.numThreads) ] diff --git a/src/arch/arm/kvm/BaseArmKvmCPU.py b/src/arch/arm/kvm/BaseArmKvmCPU.py index 63a11d8f60..364fe447a1 100644 --- a/src/arch/arm/kvm/BaseArmKvmCPU.py +++ b/src/arch/arm/kvm/BaseArmKvmCPU.py @@ -34,10 +34,14 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from m5.params import * +from m5.objects.ArmCPU import ArmCPU +from m5.objects.ArmMMU import ArmMMU from m5.objects.BaseKvmCPU import BaseKvmCPU -class BaseArmKvmCPU(BaseKvmCPU): +class BaseArmKvmCPU(BaseKvmCPU, ArmCPU): type = 'BaseArmKvmCPU' cxx_header = "arch/arm/kvm/base_cpu.hh" cxx_class = 'gem5::BaseArmKvmCPU' abstract = True + + mmu = ArmMMU() diff --git a/src/arch/mips/AtomicSimpleCPU.py b/src/arch/mips/AtomicSimpleCPU.py new file mode 100644 index 0000000000..93c289aadf --- /dev/null +++ b/src/arch/mips/AtomicSimpleCPU.py @@ -0,0 +1,28 @@ +# Copyright 2021 Google, Inc. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.objects.MipsCPU import MipsAtomicSimpleCPU + +AtomicSimpleCPU = MipsAtomicSimpleCPU diff --git a/src/cpu/minor/SConsopts b/src/arch/mips/MipsCPU.py similarity index 62% rename from src/cpu/minor/SConsopts rename to src/arch/mips/MipsCPU.py index 16ff599cb6..61b7fd23b5 100644 --- a/src/cpu/minor/SConsopts +++ b/src/arch/mips/MipsCPU.py @@ -1,16 +1,4 @@ -# -*- mode:python -*- - -# Copyright (c) 2012-2014 ARM Limited -# All rights reserved. -# -# The license below extends only to copyright in the software and shall -# not be construed as granting a license to any other intellectual -# property including but not limited to intellectual property relating -# to a hardware implementation of the functionality of the software -# licensed hereunder. You may use the software subject to the license -# terms below provided that you ensure that this notice is replicated -# unmodified and in its entirety in all distributions of the software, -# modified or unmodified, in source code or in binary form. +# Copyright 2021 Google, Inc. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are @@ -35,6 +23,29 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -Import('*') +from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU +from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU +from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU +from m5.objects.BaseO3CPU import BaseO3CPU +from m5.objects.MipsDecoder import MipsDecoder +from m5.objects.MipsMMU import MipsMMU +from m5.objects.MipsInterrupts import MipsInterrupts +from m5.objects.MipsISA import MipsISA -main.Append(ALL_CPU_MODELS=['MinorCPU']) +class MipsCPU: + ArchDecoder = MipsDecoder + ArchMMU = MipsMMU + ArchInterrupts = MipsInterrupts + ArchISA = MipsISA + +class MipsAtomicSimpleCPU(BaseAtomicSimpleCPU, MipsCPU): + mmu = MipsMMU() + +class MipsNonCachingSimpleCPU(BaseNonCachingSimpleCPU, MipsCPU): + mmu = MipsMMU() + +class MipsTimingSimpleCPU(BaseTimingSimpleCPU, MipsCPU): + mmu = MipsMMU() + +class MipsO3CPU(BaseO3CPU, MipsCPU): + mmu = MipsMMU() diff --git a/src/arch/mips/NonCachingSimpleCPU.py b/src/arch/mips/NonCachingSimpleCPU.py new file mode 100644 index 0000000000..b3753475e1 --- /dev/null +++ b/src/arch/mips/NonCachingSimpleCPU.py @@ -0,0 +1,28 @@ +# Copyright 2021 Google, Inc. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.objects.MipsCPU import MipsNonCachingSimpleCPU + +NonCachingSimpleCPU = MipsNonCachingSimpleCPU diff --git a/src/cpu/checker/SConsopts b/src/arch/mips/O3CPU.py similarity index 89% rename from src/cpu/checker/SConsopts rename to src/arch/mips/O3CPU.py index 5a7a873819..8f7b14cfc6 100644 --- a/src/cpu/checker/SConsopts +++ b/src/arch/mips/O3CPU.py @@ -1,7 +1,4 @@ -# -*- mode:python -*- - -# Copyright (c) 2003-2006 The Regents of The University of Michigan -# All rights reserved. +# Copyright 2021 Google, Inc. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are @@ -26,6 +23,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -Import('*') +from m5.objects.MipsCPU import MipsO3CPU -main.Append(ALL_CPU_MODELS=['CheckerCPU']) +O3CPU = MipsO3CPU + +# Deprecated +DerivO3CPU = O3CPU diff --git a/src/arch/mips/SConscript b/src/arch/mips/SConscript index 2a4110a247..4f09e49641 100644 --- a/src/arch/mips/SConscript +++ b/src/arch/mips/SConscript @@ -51,6 +51,13 @@ SimObject('MipsSeWorkload.py', sim_objects=['MipsSEWorkload', 'MipsEmuLinux'], tags='mips isa') SimObject('MipsTLB.py', sim_objects=['MipsTLB'], tags='mips isa') +SimObject('MipsCPU.py', sim_objects=[], tags='mips isa') +if env['TARGET_ISA'] == 'mips': + SimObject('AtomicSimpleCPU.py', sim_objects=[], tags='mips isa') + SimObject('TimingSimpleCPU.py', sim_objects=[], tags='mips isa') + SimObject('NonCachingSimpleCPU.py', sim_objects=[], tags='mips isa') + SimObject('O3CPU.py', sim_objects=[], tags='mips isa') + DebugFlag('MipsPRA', tags='mips isa') ISADesc('isa/main.isa', tags='mips isa') diff --git a/src/arch/mips/TimingSimpleCPU.py b/src/arch/mips/TimingSimpleCPU.py new file mode 100644 index 0000000000..af687a7d1a --- /dev/null +++ b/src/arch/mips/TimingSimpleCPU.py @@ -0,0 +1,28 @@ +# Copyright 2021 Google, Inc. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.objects.MipsCPU import MipsTimingSimpleCPU + +TimingSimpleCPU = MipsTimingSimpleCPU diff --git a/src/arch/power/AtomicSimpleCPU.py b/src/arch/power/AtomicSimpleCPU.py new file mode 100644 index 0000000000..55b6b960b1 --- /dev/null +++ b/src/arch/power/AtomicSimpleCPU.py @@ -0,0 +1,28 @@ +# Copyright 2021 Google, Inc. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.objects.PowerCPU import PowerAtomicSimpleCPU + +AtomicSimpleCPU = PowerAtomicSimpleCPU diff --git a/src/arch/power/NonCachingSimpleCPU.py b/src/arch/power/NonCachingSimpleCPU.py new file mode 100644 index 0000000000..171a90d9a1 --- /dev/null +++ b/src/arch/power/NonCachingSimpleCPU.py @@ -0,0 +1,28 @@ +# Copyright 2021 Google, Inc. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.objects.PowerCPU import PowerNonCachingSimpleCPU + +NonCachingSimpleCPU = PowerNonCachingSimpleCPU diff --git a/src/cpu/simple/SConsopts b/src/arch/power/O3CPU.py similarity index 88% rename from src/cpu/simple/SConsopts rename to src/arch/power/O3CPU.py index f12fee2b78..fdb63edc9e 100644 --- a/src/cpu/simple/SConsopts +++ b/src/arch/power/O3CPU.py @@ -1,7 +1,4 @@ -# -*- mode:python -*- - -# Copyright (c) 2006 The Regents of The University of Michigan -# All rights reserved. +# Copyright 2021 Google, Inc. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are @@ -26,6 +23,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -Import('*') +from m5.objects.PowerCPU import PowerO3CPU -main.Append(ALL_CPU_MODELS=['AtomicSimpleCPU', 'TimingSimpleCPU']) +O3CPU = PowerO3CPU + +# Deprecated +DerivO3CPU = O3CPU diff --git a/src/arch/power/PowerCPU.py b/src/arch/power/PowerCPU.py new file mode 100644 index 0000000000..bf7dc91d2e --- /dev/null +++ b/src/arch/power/PowerCPU.py @@ -0,0 +1,51 @@ +# Copyright 2021 Google, Inc. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU +from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU +from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU +from m5.objects.BaseO3CPU import BaseO3CPU +from m5.objects.PowerDecoder import PowerDecoder +from m5.objects.PowerMMU import PowerMMU +from m5.objects.PowerInterrupts import PowerInterrupts +from m5.objects.PowerISA import PowerISA + +class PowerCPU: + ArchDecoder = PowerDecoder + ArchMMU = PowerMMU + ArchInterrupts = PowerInterrupts + ArchISA = PowerISA + +class PowerAtomicSimpleCPU(BaseAtomicSimpleCPU, PowerCPU): + mmu = PowerMMU() + +class PowerNonCachingSimpleCPU(BaseNonCachingSimpleCPU, PowerCPU): + mmu = PowerMMU() + +class PowerTimingSimpleCPU(BaseTimingSimpleCPU, PowerCPU): + mmu = PowerMMU() + +class PowerO3CPU(BaseO3CPU, PowerCPU): + mmu = PowerMMU() diff --git a/src/arch/power/SConscript b/src/arch/power/SConscript index 7dd408933a..b20a4c9339 100644 --- a/src/arch/power/SConscript +++ b/src/arch/power/SConscript @@ -55,6 +55,13 @@ SimObject('PowerSeWorkload.py', sim_objects=[ 'PowerSEWorkload', 'PowerEmuLinux'], tags='power isa') SimObject('PowerTLB.py', sim_objects=['PowerTLB'], tags='power isa') +SimObject('PowerCPU.py', sim_objects=[], tags='power isa') +if env['TARGET_ISA'] == 'power': + SimObject('AtomicSimpleCPU.py', sim_objects=[], tags='power isa') + SimObject('TimingSimpleCPU.py', sim_objects=[], tags='power isa') + SimObject('NonCachingSimpleCPU.py', sim_objects=[], tags='power isa') + SimObject('O3CPU.py', sim_objects=[], tags='power isa') + DebugFlag('Power', tags='power isa') ISADesc('isa/main.isa', tags='power isa') diff --git a/src/arch/power/TimingSimpleCPU.py b/src/arch/power/TimingSimpleCPU.py new file mode 100644 index 0000000000..5a9cfa7052 --- /dev/null +++ b/src/arch/power/TimingSimpleCPU.py @@ -0,0 +1,28 @@ +# Copyright 2021 Google, Inc. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.objects.PowerCPU import PowerTimingSimpleCPU + +TimingSimpleCPU = PowerTimingSimpleCPU diff --git a/src/arch/riscv/AtomicSimpleCPU.py b/src/arch/riscv/AtomicSimpleCPU.py new file mode 100644 index 0000000000..f471b64420 --- /dev/null +++ b/src/arch/riscv/AtomicSimpleCPU.py @@ -0,0 +1,28 @@ +# Copyright 2021 Google, Inc. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.objects.RiscvCPU import RiscvAtomicSimpleCPU + +AtomicSimpleCPU = RiscvAtomicSimpleCPU diff --git a/src/arch/riscv/MinorCPU.py b/src/arch/riscv/MinorCPU.py new file mode 100644 index 0000000000..5254bada24 --- /dev/null +++ b/src/arch/riscv/MinorCPU.py @@ -0,0 +1,28 @@ +# Copyright 2021 Google, Inc. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.objects.RiscvCPU import RiscvMinorCPU + +MinorCPU = RiscvMinorCPU diff --git a/src/arch/riscv/NonCachingSimpleCPU.py b/src/arch/riscv/NonCachingSimpleCPU.py new file mode 100644 index 0000000000..f7dcebf3c6 --- /dev/null +++ b/src/arch/riscv/NonCachingSimpleCPU.py @@ -0,0 +1,28 @@ +# Copyright 2021 Google, Inc. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.objects.RiscvCPU import RiscvNonCachingSimpleCPU + +NonCachingSimpleCPU = RiscvNonCachingSimpleCPU diff --git a/src/cpu/SConsopts b/src/arch/riscv/O3CPU.py similarity index 86% rename from src/cpu/SConsopts rename to src/arch/riscv/O3CPU.py index c39d1eb010..74e658b0db 100644 --- a/src/cpu/SConsopts +++ b/src/arch/riscv/O3CPU.py @@ -1,4 +1,4 @@ -# Copyright 2020 Google, Inc. +# Copyright 2021 Google, Inc. # # Redistribution and use in source and binary forms, with or without # modification, are permitted provided that the following conditions are @@ -23,9 +23,9 @@ # (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -Import('*') +from m5.objects.RiscvCPU import RiscvO3CPU -def add_cpu_models_var(): - sticky_vars.Add(ListVariable('CPU_MODELS', 'CPU models', [], - sorted(set(main.Split('${ALL_CPU_MODELS}'))))) -AfterSConsopts(add_cpu_models_var) +O3CPU = RiscvO3CPU + +# Deprecated +DerivO3CPU = O3CPU diff --git a/src/arch/riscv/RiscvCPU.py b/src/arch/riscv/RiscvCPU.py new file mode 100644 index 0000000000..36c2920713 --- /dev/null +++ b/src/arch/riscv/RiscvCPU.py @@ -0,0 +1,55 @@ +# Copyright 2021 Google, Inc. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU +from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU +from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU +from m5.objects.BaseO3CPU import BaseO3CPU +from m5.objects.BaseMinorCPU import BaseMinorCPU +from m5.objects.RiscvDecoder import RiscvDecoder +from m5.objects.RiscvMMU import RiscvMMU +from m5.objects.RiscvInterrupts import RiscvInterrupts +from m5.objects.RiscvISA import RiscvISA + +class RiscvCPU: + ArchDecoder = RiscvDecoder + ArchMMU = RiscvMMU + ArchInterrupts = RiscvInterrupts + ArchISA = RiscvISA + +class RiscvAtomicSimpleCPU(BaseAtomicSimpleCPU, RiscvCPU): + mmu = RiscvMMU() + +class RiscvNonCachingSimpleCPU(BaseNonCachingSimpleCPU, RiscvCPU): + mmu = RiscvMMU() + +class RiscvTimingSimpleCPU(BaseTimingSimpleCPU, RiscvCPU): + mmu = RiscvMMU() + +class RiscvO3CPU(BaseO3CPU, RiscvCPU): + mmu = RiscvMMU() + +class RiscvMinorCPU(BaseMinorCPU, RiscvCPU): + mmu = RiscvMMU() diff --git a/src/arch/riscv/SConscript b/src/arch/riscv/SConscript index 8b7942e40d..66a983ade8 100644 --- a/src/arch/riscv/SConscript +++ b/src/arch/riscv/SConscript @@ -74,6 +74,14 @@ SimObject('RiscvSeWorkload.py', sim_objects=[ SimObject('RiscvTLB.py', sim_objects=['RiscvPagetableWalker', 'RiscvTLB'], tags='riscv isa') +SimObject('RiscvCPU.py', sim_objects=[], tags='riscv isa') +if env['TARGET_ISA'] == 'riscv': + SimObject('AtomicSimpleCPU.py', sim_objects=[], tags='riscv isa') + SimObject('TimingSimpleCPU.py', sim_objects=[], tags='riscv isa') + SimObject('NonCachingSimpleCPU.py', sim_objects=[], tags='riscv isa') + SimObject('O3CPU.py', sim_objects=[], tags='riscv isa') + SimObject('MinorCPU.py', sim_objects=[], tags='riscv isa') + DebugFlag('RiscvMisc', tags='riscv isa') DebugFlag('PMP', tags='riscv isa') diff --git a/src/arch/riscv/TimingSimpleCPU.py b/src/arch/riscv/TimingSimpleCPU.py new file mode 100644 index 0000000000..03d530f5ad --- /dev/null +++ b/src/arch/riscv/TimingSimpleCPU.py @@ -0,0 +1,28 @@ +# Copyright 2021 Google, Inc. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.objects.RiscvCPU import RiscvTimingSimpleCPU + +TimingSimpleCPU = RiscvTimingSimpleCPU diff --git a/src/arch/sparc/AtomicSimpleCPU.py b/src/arch/sparc/AtomicSimpleCPU.py new file mode 100644 index 0000000000..6f57f88064 --- /dev/null +++ b/src/arch/sparc/AtomicSimpleCPU.py @@ -0,0 +1,28 @@ +# Copyright 2021 Google, Inc. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.objects.SparcCPU import SparcAtomicSimpleCPU + +AtomicSimpleCPU = SparcAtomicSimpleCPU diff --git a/src/arch/sparc/NonCachingSimpleCPU.py b/src/arch/sparc/NonCachingSimpleCPU.py new file mode 100644 index 0000000000..5d8b5ffcdb --- /dev/null +++ b/src/arch/sparc/NonCachingSimpleCPU.py @@ -0,0 +1,28 @@ +# Copyright 2021 Google, Inc. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.objects.SparcCPU import SparcNonCachingSimpleCPU + +NonCachingSimpleCPU = SparcNonCachingSimpleCPU diff --git a/src/arch/sparc/O3CPU.py b/src/arch/sparc/O3CPU.py new file mode 100644 index 0000000000..486c6c8bc7 --- /dev/null +++ b/src/arch/sparc/O3CPU.py @@ -0,0 +1,31 @@ +# Copyright 2021 Google, Inc. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.objects.SparcCPU import SparcO3CPU + +O3CPU = SparcO3CPU + +# Deprecated +DerivO3CPU = O3CPU diff --git a/src/arch/sparc/SConscript b/src/arch/sparc/SConscript index c25d33f681..fe3a037231 100644 --- a/src/arch/sparc/SConscript +++ b/src/arch/sparc/SConscript @@ -56,6 +56,13 @@ SimObject('SparcSeWorkload.py', sim_objects=[ 'SparcSEWorkload', 'SparcEmuLinux'], tags='sparc isa') SimObject('SparcTLB.py', sim_objects=['SparcTLB'], tags='sparc isa') +SimObject('SparcCPU.py', sim_objects=[], tags='sparc isa') +if env['TARGET_ISA'] == 'sparc': + SimObject('AtomicSimpleCPU.py', sim_objects=[], tags='sparc isa') + SimObject('TimingSimpleCPU.py', sim_objects=[], tags='sparc isa') + SimObject('NonCachingSimpleCPU.py', sim_objects=[], tags='sparc isa') + SimObject('O3CPU.py', sim_objects=[], tags='sparc isa') + DebugFlag('Sparc', "Generic SPARC ISA stuff", tags='sparc isa') DebugFlag('RegisterWindows', "Register window manipulation", tags='sparc isa') diff --git a/src/arch/sparc/SparcCPU.py b/src/arch/sparc/SparcCPU.py new file mode 100644 index 0000000000..b6c33059df --- /dev/null +++ b/src/arch/sparc/SparcCPU.py @@ -0,0 +1,51 @@ +# Copyright 2021 Google, Inc. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU +from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU +from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU +from m5.objects.BaseO3CPU import BaseO3CPU +from m5.objects.SparcDecoder import SparcDecoder +from m5.objects.SparcMMU import SparcMMU +from m5.objects.SparcInterrupts import SparcInterrupts +from m5.objects.SparcISA import SparcISA + +class SparcCPU: + ArchDecoder = SparcDecoder + ArchMMU = SparcMMU + ArchInterrupts = SparcInterrupts + ArchISA = SparcISA + +class SparcAtomicSimpleCPU(BaseAtomicSimpleCPU, SparcCPU): + mmu = SparcMMU() + +class SparcNonCachingSimpleCPU(BaseNonCachingSimpleCPU, SparcCPU): + mmu = SparcMMU() + +class SparcTimingSimpleCPU(BaseTimingSimpleCPU, SparcCPU): + mmu = SparcMMU() + +class SparcO3CPU(BaseO3CPU, SparcCPU): + mmu = SparcMMU() diff --git a/src/arch/sparc/TimingSimpleCPU.py b/src/arch/sparc/TimingSimpleCPU.py new file mode 100644 index 0000000000..0471c1882b --- /dev/null +++ b/src/arch/sparc/TimingSimpleCPU.py @@ -0,0 +1,28 @@ +# Copyright 2021 Google, Inc. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.objects.SparcCPU import SparcTimingSimpleCPU + +TimingSimpleCPU = SparcTimingSimpleCPU diff --git a/src/arch/x86/AtomicSimpleCPU.py b/src/arch/x86/AtomicSimpleCPU.py new file mode 100644 index 0000000000..432346102c --- /dev/null +++ b/src/arch/x86/AtomicSimpleCPU.py @@ -0,0 +1,28 @@ +# Copyright 2021 Google, Inc. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.objects.X86CPU import X86AtomicSimpleCPU + +AtomicSimpleCPU = X86AtomicSimpleCPU diff --git a/src/arch/x86/NonCachingSimpleCPU.py b/src/arch/x86/NonCachingSimpleCPU.py new file mode 100644 index 0000000000..0559bf6082 --- /dev/null +++ b/src/arch/x86/NonCachingSimpleCPU.py @@ -0,0 +1,28 @@ +# Copyright 2021 Google, Inc. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.objects.X86CPU import X86NonCachingSimpleCPU + +NonCachingSimpleCPU = X86NonCachingSimpleCPU diff --git a/src/arch/x86/O3CPU.py b/src/arch/x86/O3CPU.py new file mode 100644 index 0000000000..a81acf1234 --- /dev/null +++ b/src/arch/x86/O3CPU.py @@ -0,0 +1,31 @@ +# Copyright 2021 Google, Inc. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.objects.X86CPU import X86O3CPU + +O3CPU = X86O3CPU + +# Deprecated +DerivO3CPU = O3CPU diff --git a/src/arch/x86/SConscript b/src/arch/x86/SConscript index d1ec5499ea..ad3d698bd7 100644 --- a/src/arch/x86/SConscript +++ b/src/arch/x86/SConscript @@ -72,6 +72,13 @@ SimObject('X86NativeTrace.py', sim_objects=['X86NativeTrace'], tags='x86 isa') SimObject('X86TLB.py', sim_objects=['X86PagetableWalker', 'X86TLB'], tags='x86 isa') +SimObject('X86CPU.py', sim_objects=[], tags='x86 isa') +if env['TARGET_ISA'] == 'x86': + SimObject('AtomicSimpleCPU.py', sim_objects=[], tags='x86 isa') + SimObject('TimingSimpleCPU.py', sim_objects=[], tags='x86 isa') + SimObject('NonCachingSimpleCPU.py', sim_objects=[], tags='x86 isa') + SimObject('O3CPU.py', sim_objects=[], tags='x86 isa') + DebugFlag('LocalApic', "Local APIC debugging", tags='x86 isa') DebugFlag('X86', "Generic X86 ISA debugging", tags='x86 isa') DebugFlag('ACPI', "ACPI debugging", tags='x86 isa') diff --git a/src/arch/x86/TimingSimpleCPU.py b/src/arch/x86/TimingSimpleCPU.py new file mode 100644 index 0000000000..cf6c529b13 --- /dev/null +++ b/src/arch/x86/TimingSimpleCPU.py @@ -0,0 +1,28 @@ +# Copyright 2021 Google, Inc. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.objects.X86CPU import X86TimingSimpleCPU + +TimingSimpleCPU = X86TimingSimpleCPU diff --git a/src/arch/x86/X86CPU.py b/src/arch/x86/X86CPU.py new file mode 100644 index 0000000000..0b46c94c6e --- /dev/null +++ b/src/arch/x86/X86CPU.py @@ -0,0 +1,62 @@ +# Copyright 2021 Google, Inc. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.proxy import Self + +from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU +from m5.objects.BaseNonCachingSimpleCPU import BaseNonCachingSimpleCPU +from m5.objects.BaseTimingSimpleCPU import BaseTimingSimpleCPU +from m5.objects.BaseO3CPU import BaseO3CPU +from m5.objects.X86Decoder import X86Decoder +from m5.objects.X86MMU import X86MMU +from m5.objects.X86LocalApic import X86LocalApic +from m5.objects.X86ISA import X86ISA + +class X86CPU: + ArchDecoder = X86Decoder + ArchMMU = X86MMU + ArchInterrupts = X86LocalApic + ArchISA = X86ISA + +class X86AtomicSimpleCPU(BaseAtomicSimpleCPU, X86CPU): + mmu = X86MMU() + +class X86NonCachingSimpleCPU(BaseNonCachingSimpleCPU, X86CPU): + mmu = X86MMU() + +class X86TimingSimpleCPU(BaseTimingSimpleCPU, X86CPU): + mmu = X86MMU() + +class X86O3CPU(BaseO3CPU, X86CPU): + mmu = X86MMU() + needsTSO = True + + # For x86, each CC reg is used to hold only a subset of the + # flags, so we need 4-5 times the number of CC regs as + # physical integer regs to be sure we don't run out. In + # typical real machines, CC regs are not explicitly renamed + # (it's a side effect of int reg renaming), so they should + # never be the bottleneck here. + numPhysCCRegs = Self.numPhysIntRegs * 5 diff --git a/src/arch/x86/kvm/X86KvmCPU.py b/src/arch/x86/kvm/X86KvmCPU.py index 54cf0f20eb..59de5eafda 100644 --- a/src/arch/x86/kvm/X86KvmCPU.py +++ b/src/arch/x86/kvm/X86KvmCPU.py @@ -28,12 +28,16 @@ from m5.params import * from m5.SimObject import * from m5.objects.BaseKvmCPU import BaseKvmCPU +from m5.objects.X86CPU import X86CPU +from m5.objects.X86MMU import X86MMU -class X86KvmCPU(BaseKvmCPU): +class X86KvmCPU(BaseKvmCPU, X86CPU): type = 'X86KvmCPU' cxx_header = "arch/x86/kvm/x86_cpu.hh" cxx_class = 'gem5::X86KvmCPU' + mmu = X86MMU() + cxx_exports = [ PyBindMethod("dumpFpuRegs"), PyBindMethod("dumpIntRegs"), diff --git a/src/cpu/BaseCPU.py b/src/cpu/BaseCPU.py index 5eeedd3642..bf4d43c359 100644 --- a/src/cpu/BaseCPU.py +++ b/src/cpu/BaseCPU.py @@ -56,41 +56,6 @@ from m5.objects.Platform import Platform default_tracer = ExeTracer() -if buildEnv['TARGET_ISA'] == 'sparc': - from m5.objects.SparcMMU import SparcMMU as ArchMMU - from m5.objects.SparcInterrupts import SparcInterrupts as ArchInterrupts - from m5.objects.SparcISA import SparcISA as ArchISA - from m5.objects.SparcDecoder import SparcDecoder as ArchDecoder -elif buildEnv['TARGET_ISA'] == 'x86': - from m5.objects.X86MMU import X86MMU as ArchMMU - from m5.objects.X86LocalApic import X86LocalApic as ArchInterrupts - from m5.objects.X86ISA import X86ISA as ArchISA - from m5.objects.X86Decoder import X86Decoder as ArchDecoder -elif buildEnv['TARGET_ISA'] == 'mips': - from m5.objects.MipsMMU import MipsMMU as ArchMMU - from m5.objects.MipsInterrupts import MipsInterrupts as ArchInterrupts - from m5.objects.MipsISA import MipsISA as ArchISA - from m5.objects.MipsDecoder import MipsDecoder as ArchDecoder -elif buildEnv['TARGET_ISA'] == 'arm': - from m5.objects.ArmMMU import ArmMMU as ArchMMU - from m5.objects.ArmInterrupts import ArmInterrupts as ArchInterrupts - from m5.objects.ArmISA import ArmISA as ArchISA - from m5.objects.ArmDecoder import ArmDecoder as ArchDecoder -elif buildEnv['TARGET_ISA'] == 'power': - from m5.objects.PowerMMU import PowerMMU as ArchMMU - from m5.objects.PowerInterrupts import PowerInterrupts as ArchInterrupts - from m5.objects.PowerISA import PowerISA as ArchISA - from m5.objects.PowerDecoder import PowerDecoder as ArchDecoder -elif buildEnv['TARGET_ISA'] == 'riscv': - from m5.objects.RiscvMMU import RiscvMMU as ArchMMU - from m5.objects.RiscvInterrupts import RiscvInterrupts as ArchInterrupts - from m5.objects.RiscvISA import RiscvISA as ArchISA - from m5.objects.RiscvDecoder import RiscvDecoder as ArchDecoder -else: - print("Don't know what object types to use for ISA %s" % - buildEnv['TARGET_ISA']) - sys.exit(1) - class BaseCPU(ClockedObject): type = 'BaseCPU' abstract = True @@ -155,7 +120,7 @@ class BaseCPU(ClockedObject): workload = VectorParam.Process([], "processes to run") - mmu = Param.BaseMMU(ArchMMU(), "CPU memory management unit") + mmu = Param.BaseMMU(NULL, "CPU memory management unit") interrupts = VectorParam.BaseInterrupts([], "Interrupt Controller") isa = VectorParam.BaseISA([], "ISA instance") decoder = VectorParam.InstDecoder([], "Decoder instance") @@ -183,7 +148,8 @@ class BaseCPU(ClockedObject): _uncached_interrupt_request_ports = [] def createInterruptController(self): - self.interrupts = [ArchInterrupts() for i in range(self.numThreads)] + self.interrupts = [ + self.ArchInterrupts() for i in range(self.numThreads)] def connectCachedPorts(self, in_ports): for p in self._cached_ports: @@ -217,13 +183,13 @@ class BaseCPU(ClockedObject): self._cached_ports += ["itb_walker_cache.mem_side", \ "dtb_walker_cache.mem_side"] else: - self._cached_ports += ArchMMU.walkerPorts() + self._cached_ports += self.ArchMMU.walkerPorts() # Checker doesn't need its own tlb caches because it does # functional accesses only if self.checker != NULL: self._cached_ports += [ "checker." + port - for port in ArchMMU.walkerPorts() ] + for port in self.ArchMMU.walkerPorts() ] def addTwoLevelCacheHierarchy(self, ic, dc, l2c, iwc=None, dwc=None, xbar=None): @@ -238,14 +204,14 @@ class BaseCPU(ClockedObject): # If no ISAs have been created, assume that the user wants the # default ISA. if len(self.isa) == 0: - self.isa = list([ ArchISA() for i in range(self.numThreads) ]) + self.isa = [ self.ArchISA() for i in range(self.numThreads) ] else: if len(self.isa) != int(self.numThreads): raise RuntimeError("Number of ISA instances doesn't " "match thread count") if len(self.decoder) != 0: raise RuntimeError("Decoders should not be set up manually") - self.decoder = list([ ArchDecoder(isa=isa) for isa in self.isa ]) + self.decoder = list([ self.ArchDecoder(isa=isa) for isa in self.isa ]) if self.checker != NULL: self.checker.createThreads() @@ -308,18 +274,18 @@ class BaseCPU(ClockedObject): super().__init__(**kwargs) self.power_state.possible_states=['ON', 'CLK_GATED', 'OFF'] - self._cached_ports = self._cached_ports + ArchMMU.walkerPorts() + self._cached_ports = self._cached_ports + self.ArchMMU.walkerPorts() # Practically speaking, these ports will exist on the x86 interrupt # controller class. - if "pio" in ArchInterrupts._ports: + if "pio" in self.ArchInterrupts._ports: self._uncached_interrupt_response_ports = \ self._uncached_interrupt_response_ports + ["interrupts[0].pio"] - if "int_responder" in ArchInterrupts._ports: + if "int_responder" in self.ArchInterrupts._ports: self._uncached_interrupt_response_ports = \ self._uncached_interrupt_response_ports + [ "interrupts[0].int_responder"] - if "int_requestor" in ArchInterrupts._ports: + if "int_requestor" in self.ArchInterrupts._ports: self._uncached_interrupt_request_ports = \ self._uncached_interrupt_request_ports + [ "interrupts[0].int_requestor"] diff --git a/src/cpu/minor/MinorCPU.py b/src/cpu/minor/BaseMinorCPU.py similarity index 99% rename from src/cpu/minor/MinorCPU.py rename to src/cpu/minor/BaseMinorCPU.py index 5b360ca249..ac26743a7d 100644 --- a/src/cpu/minor/MinorCPU.py +++ b/src/cpu/minor/BaseMinorCPU.py @@ -184,8 +184,8 @@ class MinorDefaultFUPool(MinorFUPool): class ThreadPolicy(Enum): vals = ['SingleThreaded', 'RoundRobin', 'Random'] -class MinorCPU(BaseCPU): - type = 'MinorCPU' +class BaseMinorCPU(BaseCPU): + type = 'BaseMinorCPU' cxx_header = "cpu/minor/cpu.hh" cxx_class = 'gem5::MinorCPU' diff --git a/src/cpu/minor/SConscript b/src/cpu/minor/SConscript index 090ac442e4..db4b1bfb59 100644 --- a/src/cpu/minor/SConscript +++ b/src/cpu/minor/SConscript @@ -40,10 +40,10 @@ Import('*') -if 'MinorCPU' in env['CPU_MODELS']: - SimObject('MinorCPU.py', sim_objects=[ +if env['TARGET_ISA'] != 'null': + SimObject('BaseMinorCPU.py', sim_objects=[ 'MinorOpClass', 'MinorOpClassSet', 'MinorFUTiming', 'MinorFU', - 'MinorFUPool', 'MinorCPU'], + 'MinorFUPool', 'BaseMinorCPU'], enums=['ThreadPolicy']) Source('activity.cc') diff --git a/src/cpu/minor/cpu.cc b/src/cpu/minor/cpu.cc index 0bc26e3c4c..2e554aaa0b 100644 --- a/src/cpu/minor/cpu.cc +++ b/src/cpu/minor/cpu.cc @@ -47,7 +47,7 @@ namespace gem5 { -MinorCPU::MinorCPU(const MinorCPUParams ¶ms) : +MinorCPU::MinorCPU(const BaseMinorCPUParams ¶ms) : BaseCPU(params), threadPolicy(params.threadPolicy), stats(this) diff --git a/src/cpu/minor/cpu.hh b/src/cpu/minor/cpu.hh index 9ed93db463..b5b04ae908 100644 --- a/src/cpu/minor/cpu.hh +++ b/src/cpu/minor/cpu.hh @@ -51,7 +51,7 @@ #include "cpu/minor/stats.hh" #include "cpu/simple_thread.hh" #include "enums/ThreadPolicy.hh" -#include "params/MinorCPU.hh" +#include "params/BaseMinorCPU.hh" namespace gem5 { @@ -126,7 +126,7 @@ class MinorCPU : public BaseCPU Port &getInstPort() override; public: - MinorCPU(const MinorCPUParams ¶ms); + MinorCPU(const BaseMinorCPUParams ¶ms); ~MinorCPU(); diff --git a/src/cpu/minor/decode.cc b/src/cpu/minor/decode.cc index 5adf2cacfc..53c02f321d 100644 --- a/src/cpu/minor/decode.cc +++ b/src/cpu/minor/decode.cc @@ -51,7 +51,7 @@ namespace minor Decode::Decode(const std::string &name, MinorCPU &cpu_, - const MinorCPUParams ¶ms, + const BaseMinorCPUParams ¶ms, Latch::Output inp_, Latch::Input out_, std::vector> &next_stage_input_buffer) : diff --git a/src/cpu/minor/decode.hh b/src/cpu/minor/decode.hh index 6e9cb62fbd..156b92038c 100644 --- a/src/cpu/minor/decode.hh +++ b/src/cpu/minor/decode.hh @@ -141,7 +141,7 @@ class Decode : public Named public: Decode(const std::string &name, MinorCPU &cpu_, - const MinorCPUParams ¶ms, + const BaseMinorCPUParams ¶ms, Latch::Output inp_, Latch::Input out_, std::vector> &next_stage_input_buffer); diff --git a/src/cpu/minor/execute.cc b/src/cpu/minor/execute.cc index c09f3be741..f7022d1234 100644 --- a/src/cpu/minor/execute.cc +++ b/src/cpu/minor/execute.cc @@ -63,7 +63,7 @@ namespace minor Execute::Execute(const std::string &name_, MinorCPU &cpu_, - const MinorCPUParams ¶ms, + const BaseMinorCPUParams ¶ms, Latch::Output inp_, Latch::Input out_) : Named(name_), diff --git a/src/cpu/minor/execute.hh b/src/cpu/minor/execute.hh index 9d184f7428..521b3b6cbb 100644 --- a/src/cpu/minor/execute.hh +++ b/src/cpu/minor/execute.hh @@ -326,7 +326,7 @@ class Execute : public Named public: Execute(const std::string &name_, MinorCPU &cpu_, - const MinorCPUParams ¶ms, + const BaseMinorCPUParams ¶ms, Latch::Output inp_, Latch::Input out_); diff --git a/src/cpu/minor/fetch1.cc b/src/cpu/minor/fetch1.cc index 482933995c..daf8d560b3 100644 --- a/src/cpu/minor/fetch1.cc +++ b/src/cpu/minor/fetch1.cc @@ -60,7 +60,7 @@ namespace minor Fetch1::Fetch1(const std::string &name_, MinorCPU &cpu_, - const MinorCPUParams ¶ms, + const BaseMinorCPUParams ¶ms, Latch::Output inp_, Latch::Input out_, Latch::Output prediction_, diff --git a/src/cpu/minor/fetch1.hh b/src/cpu/minor/fetch1.hh index bd8ad7d224..e33eb0493b 100644 --- a/src/cpu/minor/fetch1.hh +++ b/src/cpu/minor/fetch1.hh @@ -386,7 +386,7 @@ class Fetch1 : public Named public: Fetch1(const std::string &name_, MinorCPU &cpu_, - const MinorCPUParams ¶ms, + const BaseMinorCPUParams ¶ms, Latch::Output inp_, Latch::Input out_, Latch::Output prediction_, diff --git a/src/cpu/minor/fetch2.cc b/src/cpu/minor/fetch2.cc index c5a7045268..b506bc0428 100644 --- a/src/cpu/minor/fetch2.cc +++ b/src/cpu/minor/fetch2.cc @@ -58,7 +58,7 @@ namespace minor Fetch2::Fetch2(const std::string &name, MinorCPU &cpu_, - const MinorCPUParams ¶ms, + const BaseMinorCPUParams ¶ms, Latch::Output inp_, Latch::Output branchInp_, Latch::Input predictionOut_, diff --git a/src/cpu/minor/fetch2.hh b/src/cpu/minor/fetch2.hh index 2eb8a772f1..85012bf927 100644 --- a/src/cpu/minor/fetch2.hh +++ b/src/cpu/minor/fetch2.hh @@ -52,7 +52,7 @@ #include "cpu/minor/cpu.hh" #include "cpu/minor/pipe_data.hh" #include "cpu/pred/bpred_unit.hh" -#include "params/MinorCPU.hh" +#include "params/BaseMinorCPU.hh" namespace gem5 { @@ -201,7 +201,7 @@ class Fetch2 : public Named public: Fetch2(const std::string &name, MinorCPU &cpu_, - const MinorCPUParams ¶ms, + const BaseMinorCPUParams ¶ms, Latch::Output inp_, Latch::Output branchInp_, Latch::Input predictionOut_, diff --git a/src/cpu/minor/pipeline.cc b/src/cpu/minor/pipeline.cc index 358f4dfae9..e94181fcd8 100644 --- a/src/cpu/minor/pipeline.cc +++ b/src/cpu/minor/pipeline.cc @@ -55,7 +55,7 @@ GEM5_DEPRECATED_NAMESPACE(Minor, minor); namespace minor { -Pipeline::Pipeline(MinorCPU &cpu_, const MinorCPUParams ¶ms) : +Pipeline::Pipeline(MinorCPU &cpu_, const BaseMinorCPUParams ¶ms) : Ticked(cpu_, &(cpu_.BaseCPU::baseStats.numCycles)), cpu(cpu_), allow_idling(params.enableIdling), diff --git a/src/cpu/minor/pipeline.hh b/src/cpu/minor/pipeline.hh index f2eab5de18..ce0ae07d3e 100644 --- a/src/cpu/minor/pipeline.hh +++ b/src/cpu/minor/pipeline.hh @@ -51,7 +51,7 @@ #include "cpu/minor/execute.hh" #include "cpu/minor/fetch1.hh" #include "cpu/minor/fetch2.hh" -#include "params/MinorCPU.hh" +#include "params/BaseMinorCPU.hh" #include "sim/ticked_object.hh" namespace gem5 @@ -109,7 +109,7 @@ class Pipeline : public Ticked bool needToSignalDrained; public: - Pipeline(MinorCPU &cpu_, const MinorCPUParams ¶ms); + Pipeline(MinorCPU &cpu_, const BaseMinorCPUParams ¶ms); public: /** Wake up the Fetch unit. This is needed on thread activation esp. diff --git a/src/cpu/o3/O3CPU.py b/src/cpu/o3/BaseO3CPU.py similarity index 78% rename from src/cpu/o3/O3CPU.py rename to src/cpu/o3/BaseO3CPU.py index fb1a9dc9db..c58f9fee38 100644 --- a/src/cpu/o3/O3CPU.py +++ b/src/cpu/o3/BaseO3CPU.py @@ -42,7 +42,7 @@ from m5.proxy import * from m5.objects.BaseCPU import BaseCPU from m5.objects.FUPool import * -from m5.objects.O3Checker import O3Checker +#from m5.objects.O3Checker import O3Checker from m5.objects.BranchPredictor import * class SMTFetchPolicy(ScopedEnum): @@ -54,8 +54,8 @@ class SMTQueuePolicy(ScopedEnum): class CommitPolicy(ScopedEnum): vals = [ 'RoundRobin', 'OldestReady' ] -class O3CPU(BaseCPU): - type = 'O3CPU' +class BaseO3CPU(BaseCPU): + type = 'BaseO3CPU' cxx_class = 'gem5::o3::CPU' cxx_header = 'cpu/o3/dyn_inst.hh' @@ -120,40 +120,36 @@ class O3CPU(BaseCPU): trapLatency = Param.Cycles(13, "Trap latency") fetchTrapLatency = Param.Cycles(1, "Fetch trap latency") - backComSize = Param.Unsigned(5, "Time buffer size for backwards communication") - forwardComSize = Param.Unsigned(5, "Time buffer size for forward communication") + backComSize = Param.Unsigned(5, + "Time buffer size for backwards communication") + forwardComSize = Param.Unsigned(5, + "Time buffer size for forward communication") LQEntries = Param.Unsigned(32, "Number of load queue entries") SQEntries = Param.Unsigned(32, "Number of store queue entries") - LSQDepCheckShift = Param.Unsigned(4, "Number of places to shift addr before check") + LSQDepCheckShift = Param.Unsigned(4, + "Number of places to shift addr before check") LSQCheckLoads = Param.Bool(True, - "Should dependency violations be checked for loads & stores or just stores") + "Should dependency violations be checked for " + "loads & stores or just stores") store_set_clear_period = Param.Unsigned(250000, - "Number of load/store insts before the dep predictor should be invalidated") + "Number of load/store insts before the dep predictor " + "should be invalidated") LFSTSize = Param.Unsigned(1024, "Last fetched store table size") SSITSize = Param.Unsigned(1024, "Store set ID table size") numRobs = Param.Unsigned(1, "Number of Reorder Buffers"); - numPhysIntRegs = Param.Unsigned(256, "Number of physical integer registers") + numPhysIntRegs = Param.Unsigned(256, + "Number of physical integer registers") numPhysFloatRegs = Param.Unsigned(256, "Number of physical floating point " "registers") - # most ISAs don't use condition-code regs, so default is 0 - _defaultNumPhysCCRegs = 0 - if buildEnv['TARGET_ISA'] in ('arm','x86'): - # For x86, each CC reg is used to hold only a subset of the - # flags, so we need 4-5 times the number of CC regs as - # physical integer regs to be sure we don't run out. In - # typical real machines, CC regs are not explicitly renamed - # (it's a side effect of int reg renaming), so they should - # never be the bottleneck here. - _defaultNumPhysCCRegs = Self.numPhysIntRegs * 5 numPhysVecRegs = Param.Unsigned(256, "Number of physical vector " "registers") numPhysVecPredRegs = Param.Unsigned(32, "Number of physical predicate " "registers") - numPhysCCRegs = Param.Unsigned(_defaultNumPhysCCRegs, - "Number of physical cc registers") + # most ISAs don't use condition-code regs, so default is 0 + numPhysCCRegs = Param.Unsigned(0, "Number of physical cc registers") numIQEntries = Param.Unsigned(64, "Number of instruction queue entries") numROBEntries = Param.Unsigned(192, "Number of reorder buffer entries") @@ -173,25 +169,4 @@ class O3CPU(BaseCPU): branchPred = Param.BranchPredictor(TournamentBP(numThreads = Parent.numThreads), "Branch Predictor") - needsTSO = Param.Bool(buildEnv['TARGET_ISA'] == 'x86', - "Enable TSO Memory model") - - def addCheckerCpu(self): - if buildEnv['TARGET_ISA'] in ['arm']: - from m5.objects.ArmMMU import ArmMMU - - self.checker = O3Checker(workload=self.workload, - exitOnError=False, - updateOnError=True, - warnOnlyOnLoadError=True) - self.checker.mmu = ArmMMU() - self.checker.mmu.itb.size = self.mmu.itb.size - self.checker.mmu.dtb.size = self.mmu.dtb.size - self.checker.cpu_id = self.cpu_id - - else: - print("ERROR: Checker only supported under ARM ISA!") - exit(1) - -# Deprecated -DerivO3CPU = O3CPU + needsTSO = Param.Bool(False, "Enable TSO Memory model") diff --git a/src/cpu/o3/BaseO3Checker.py b/src/cpu/o3/BaseO3Checker.py new file mode 100644 index 0000000000..6365491950 --- /dev/null +++ b/src/cpu/o3/BaseO3Checker.py @@ -0,0 +1,33 @@ +# Copyright (c) 2007 The Regents of The University of Michigan +# All rights reserved. +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions are +# met: redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer; +# redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in the +# documentation and/or other materials provided with the distribution; +# neither the name of the copyright holders nor the names of its +# contributors may be used to endorse or promote products derived from +# this software without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + +from m5.params import * +from m5.objects.CheckerCPU import CheckerCPU + +class BaseO3Checker(CheckerCPU): + type = 'BaseO3Checker' + cxx_class = 'gem5::o3::Checker' + cxx_header = 'cpu/o3/checker.hh' diff --git a/src/cpu/o3/SConscript b/src/cpu/o3/SConscript index ba021a892a..a0bebb295c 100755 --- a/src/cpu/o3/SConscript +++ b/src/cpu/o3/SConscript @@ -30,10 +30,10 @@ import sys Import('*') -if 'O3CPU' in env['CPU_MODELS']: +if env['TARGET_ISA'] != 'null': SimObject('FUPool.py', sim_objects=['FUPool']) SimObject('FuncUnitConfig.py', sim_objects=[]) - SimObject('O3CPU.py', sim_objects=['O3CPU'], enums=[ + SimObject('BaseO3CPU.py', sim_objects=['BaseO3CPU'], enums=[ 'SMTFetchPolicy', 'SMTQueuePolicy', 'CommitPolicy']) Source('commit.cc') @@ -74,5 +74,5 @@ if 'O3CPU' in env['CPU_MODELS']: 'IQ', 'ROB', 'FreeList', 'LSQ', 'LSQUnit', 'StoreSet', 'MemDepUnit', 'DynInst', 'O3CPU', 'Activity', 'Scoreboard', 'Writeback' ]) - SimObject('O3Checker.py', sim_objects=['O3Checker']) + SimObject('BaseO3Checker.py', sim_objects=['BaseO3Checker']) Source('checker.cc') diff --git a/src/cpu/o3/commit.cc b/src/cpu/o3/commit.cc index d2011c56d3..97def7e59a 100644 --- a/src/cpu/o3/commit.cc +++ b/src/cpu/o3/commit.cc @@ -64,7 +64,7 @@ #include "debug/ExecFaulting.hh" #include "debug/HtmCpu.hh" #include "debug/O3PipeView.hh" -#include "params/O3CPU.hh" +#include "params/BaseO3CPU.hh" #include "sim/faults.hh" #include "sim/full_system.hh" @@ -82,7 +82,7 @@ Commit::processTrapEvent(ThreadID tid) trapSquash[tid] = true; } -Commit::Commit(CPU *_cpu, const O3CPUParams ¶ms) +Commit::Commit(CPU *_cpu, const BaseO3CPUParams ¶ms) : commitPolicy(params.smtCommitPolicy), cpu(_cpu), iewToCommitDelay(params.iewToCommitDelay), diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh index da271ededd..cf4eaf5d92 100644 --- a/src/cpu/o3/commit.hh +++ b/src/cpu/o3/commit.hh @@ -59,7 +59,7 @@ namespace gem5 { -struct O3CPUParams; +struct BaseO3CPUParams; namespace o3 { @@ -132,7 +132,7 @@ class Commit public: /** Construct a Commit with the given parameters. */ - Commit(CPU *_cpu, const O3CPUParams ¶ms); + Commit(CPU *_cpu, const BaseO3CPUParams ¶ms); /** Returns the name of the Commit. */ std::string name() const; diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 19660b2c51..c9ed6c7229 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -70,7 +70,7 @@ struct BaseCPUParams; namespace o3 { -CPU::CPU(const O3CPUParams ¶ms) +CPU::CPU(const BaseO3CPUParams ¶ms) : BaseCPU(params), mmu(params.mmu), tickEvent([this]{ tick(); }, "O3CPU tick", diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index 670b92fa0d..4de99af9b2 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -68,7 +68,7 @@ #include "cpu/base.hh" #include "cpu/simple_thread.hh" #include "cpu/timebuf.hh" -#include "params/O3CPU.hh" +#include "params/BaseO3CPU.hh" #include "sim/process.hh" namespace gem5 @@ -169,7 +169,7 @@ class CPU : public BaseCPU public: /** Constructs a CPU with the given parameters. */ - CPU(const O3CPUParams ¶ms); + CPU(const BaseO3CPUParams ¶ms); ProbePointArg *ppInstAccessComplete; ProbePointArg > *ppDataAccessComplete; diff --git a/src/cpu/o3/decode.cc b/src/cpu/o3/decode.cc index 362daee171..40c929949a 100644 --- a/src/cpu/o3/decode.cc +++ b/src/cpu/o3/decode.cc @@ -49,7 +49,7 @@ #include "debug/Activity.hh" #include "debug/Decode.hh" #include "debug/O3PipeView.hh" -#include "params/O3CPU.hh" +#include "params/BaseO3CPU.hh" #include "sim/full_system.hh" // clang complains about std::set being overloaded with Packet::set if @@ -62,7 +62,7 @@ namespace gem5 namespace o3 { -Decode::Decode(CPU *_cpu, const O3CPUParams ¶ms) +Decode::Decode(CPU *_cpu, const BaseO3CPUParams ¶ms) : cpu(_cpu), renameToDecodeDelay(params.renameToDecodeDelay), iewToDecodeDelay(params.iewToDecodeDelay), diff --git a/src/cpu/o3/decode.hh b/src/cpu/o3/decode.hh index e8c2db2174..79bacdc6c6 100644 --- a/src/cpu/o3/decode.hh +++ b/src/cpu/o3/decode.hh @@ -52,7 +52,7 @@ namespace gem5 { -struct O3CPUParams; +struct BaseO3CPUParams; namespace o3 { @@ -98,7 +98,7 @@ class Decode public: /** Decode constructor. */ - Decode(CPU *_cpu, const O3CPUParams ¶ms); + Decode(CPU *_cpu, const BaseO3CPUParams ¶ms); void startupStage(); diff --git a/src/cpu/o3/fetch.cc b/src/cpu/o3/fetch.cc index 2105900d51..5358b3313e 100644 --- a/src/cpu/o3/fetch.cc +++ b/src/cpu/o3/fetch.cc @@ -63,7 +63,7 @@ #include "debug/O3CPU.hh" #include "debug/O3PipeView.hh" #include "mem/packet.hh" -#include "params/O3CPU.hh" +#include "params/BaseO3CPU.hh" #include "sim/byteswap.hh" #include "sim/core.hh" #include "sim/eventq.hh" @@ -81,7 +81,7 @@ Fetch::IcachePort::IcachePort(Fetch *_fetch, CPU *_cpu) : {} -Fetch::Fetch(CPU *_cpu, const O3CPUParams ¶ms) +Fetch::Fetch(CPU *_cpu, const BaseO3CPUParams ¶ms) : fetchPolicy(params.smtFetchPolicy), cpu(_cpu), branchPred(nullptr), diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh index 392e7cbe4b..1ca812b8d5 100644 --- a/src/cpu/o3/fetch.hh +++ b/src/cpu/o3/fetch.hh @@ -61,7 +61,7 @@ namespace gem5 { -struct O3CPUParams; +struct BaseO3CPUParams; namespace o3 { @@ -203,7 +203,7 @@ class Fetch public: /** Fetch constructor. */ - Fetch(CPU *_cpu, const O3CPUParams ¶ms); + Fetch(CPU *_cpu, const BaseO3CPUParams ¶ms); /** Returns the name of fetch. */ std::string name() const; diff --git a/src/cpu/o3/iew.cc b/src/cpu/o3/iew.cc index 8dbd5b3376..5c507f01a4 100644 --- a/src/cpu/o3/iew.cc +++ b/src/cpu/o3/iew.cc @@ -57,7 +57,7 @@ #include "debug/Drain.hh" #include "debug/IEW.hh" #include "debug/O3PipeView.hh" -#include "params/O3CPU.hh" +#include "params/BaseO3CPU.hh" namespace gem5 { @@ -65,7 +65,7 @@ namespace gem5 namespace o3 { -IEW::IEW(CPU *_cpu, const O3CPUParams ¶ms) +IEW::IEW(CPU *_cpu, const BaseO3CPUParams ¶ms) : issueToExecQueue(params.backComSize, params.forwardComSize), cpu(_cpu), instQueue(_cpu, this, params), diff --git a/src/cpu/o3/iew.hh b/src/cpu/o3/iew.hh index ea5350d79c..80fed295df 100644 --- a/src/cpu/o3/iew.hh +++ b/src/cpu/o3/iew.hh @@ -58,7 +58,7 @@ namespace gem5 { -struct O3CPUParams; +struct BaseO3CPUParams; namespace o3 { @@ -127,7 +127,7 @@ class IEW public: /** Constructs a IEW with the given parameters. */ - IEW(CPU *_cpu, const O3CPUParams ¶ms); + IEW(CPU *_cpu, const BaseO3CPUParams ¶ms); /** Returns the name of the IEW stage. */ std::string name() const; diff --git a/src/cpu/o3/inst_queue.cc b/src/cpu/o3/inst_queue.cc index 0fac84f03b..3f900649ed 100644 --- a/src/cpu/o3/inst_queue.cc +++ b/src/cpu/o3/inst_queue.cc @@ -50,7 +50,7 @@ #include "cpu/o3/limits.hh" #include "debug/IQ.hh" #include "enums/OpClass.hh" -#include "params/O3CPU.hh" +#include "params/BaseO3CPU.hh" #include "sim/core.hh" // clang complains about std::set being overloaded with Packet::set if @@ -85,7 +85,7 @@ InstructionQueue::FUCompletion::description() const } InstructionQueue::InstructionQueue(CPU *cpu_ptr, IEW *iew_ptr, - const O3CPUParams ¶ms) + const BaseO3CPUParams ¶ms) : cpu(cpu_ptr), iewStage(iew_ptr), fuPool(params.fuPool), diff --git a/src/cpu/o3/inst_queue.hh b/src/cpu/o3/inst_queue.hh index b2d930339e..57928e7478 100644 --- a/src/cpu/o3/inst_queue.hh +++ b/src/cpu/o3/inst_queue.hh @@ -64,7 +64,7 @@ namespace gem5 { -struct O3CPUParams; +struct BaseO3CPUParams; namespace memory { @@ -130,7 +130,8 @@ class InstructionQueue }; /** Constructs an IQ. */ - InstructionQueue(CPU *cpu_ptr, IEW *iew_ptr, const O3CPUParams ¶ms); + InstructionQueue(CPU *cpu_ptr, IEW *iew_ptr, + const BaseO3CPUParams ¶ms); /** Destructs the IQ. */ ~InstructionQueue(); diff --git a/src/cpu/o3/lsq.cc b/src/cpu/o3/lsq.cc index 78999ee46b..72ecc52926 100644 --- a/src/cpu/o3/lsq.cc +++ b/src/cpu/o3/lsq.cc @@ -56,7 +56,7 @@ #include "debug/HtmCpu.hh" #include "debug/LSQ.hh" #include "debug/Writeback.hh" -#include "params/O3CPU.hh" +#include "params/BaseO3CPU.hh" namespace gem5 { @@ -68,7 +68,7 @@ LSQ::DcachePort::DcachePort(LSQ *_lsq, CPU *_cpu) : RequestPort(_cpu->name() + ".dcache_port", _cpu), lsq(_lsq), cpu(_cpu) {} -LSQ::LSQ(CPU *cpu_ptr, IEW *iew_ptr, const O3CPUParams ¶ms) +LSQ::LSQ(CPU *cpu_ptr, IEW *iew_ptr, const BaseO3CPUParams ¶ms) : cpu(cpu_ptr), iewStage(iew_ptr), _cacheBlocked(false), cacheStorePorts(params.cacheStorePorts), usedStorePorts(0), diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh index 798ceb90b3..2e9945559a 100644 --- a/src/cpu/o3/lsq.hh +++ b/src/cpu/o3/lsq.hh @@ -63,7 +63,7 @@ namespace gem5 { -struct O3CPUParams; +struct BaseO3CPUParams; namespace o3 { @@ -647,7 +647,7 @@ class LSQ }; /** Constructs an LSQ with the given parameters. */ - LSQ(CPU *cpu_ptr, IEW *iew_ptr, const O3CPUParams ¶ms); + LSQ(CPU *cpu_ptr, IEW *iew_ptr, const BaseO3CPUParams ¶ms); /** Returns the name of the LSQ. */ std::string name() const; diff --git a/src/cpu/o3/lsq_unit.cc b/src/cpu/o3/lsq_unit.cc index baf09710c5..1541d2c893 100644 --- a/src/cpu/o3/lsq_unit.cc +++ b/src/cpu/o3/lsq_unit.cc @@ -201,7 +201,7 @@ LSQUnit::LSQUnit(uint32_t lqEntries, uint32_t sqEntries) } void -LSQUnit::init(CPU *cpu_ptr, IEW *iew_ptr, const O3CPUParams ¶ms, +LSQUnit::init(CPU *cpu_ptr, IEW *iew_ptr, const BaseO3CPUParams ¶ms, LSQ *lsq_ptr, unsigned id) { lsqID = id; diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index 0d2f80f186..e68cb53404 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -67,7 +67,7 @@ namespace gem5 { -struct O3CPUParams; +struct BaseO3CPUParams; namespace o3 { @@ -223,7 +223,7 @@ class LSQUnit } /** Initializes the LSQ unit with the specified number of entries. */ - void init(CPU *cpu_ptr, IEW *iew_ptr, const O3CPUParams ¶ms, + void init(CPU *cpu_ptr, IEW *iew_ptr, const BaseO3CPUParams ¶ms, LSQ *lsq_ptr, unsigned id); /** Returns the name of the LSQ unit. */ diff --git a/src/cpu/o3/mem_dep_unit.cc b/src/cpu/o3/mem_dep_unit.cc index 11a6135b8e..bffbf2380d 100644 --- a/src/cpu/o3/mem_dep_unit.cc +++ b/src/cpu/o3/mem_dep_unit.cc @@ -38,7 +38,7 @@ #include "cpu/o3/inst_queue.hh" #include "cpu/o3/limits.hh" #include "debug/MemDepUnit.hh" -#include "params/O3CPU.hh" +#include "params/BaseO3CPU.hh" namespace gem5 { @@ -54,7 +54,7 @@ int MemDepUnit::MemDepEntry::memdep_erase = 0; MemDepUnit::MemDepUnit() : iqPtr(NULL), stats(nullptr) {} -MemDepUnit::MemDepUnit(const O3CPUParams ¶ms) +MemDepUnit::MemDepUnit(const BaseO3CPUParams ¶ms) : _name(params.name + ".memdepunit"), depPred(params.store_set_clear_period, params.SSITSize, params.LFSTSize), @@ -89,7 +89,7 @@ MemDepUnit::~MemDepUnit() } void -MemDepUnit::init(const O3CPUParams ¶ms, ThreadID tid, CPU *cpu) +MemDepUnit::init(const BaseO3CPUParams ¶ms, ThreadID tid, CPU *cpu) { DPRINTF(MemDepUnit, "Creating MemDepUnit %i object.\n",tid); diff --git a/src/cpu/o3/mem_dep_unit.hh b/src/cpu/o3/mem_dep_unit.hh index c6b270cfe1..6609f8dcad 100644 --- a/src/cpu/o3/mem_dep_unit.hh +++ b/src/cpu/o3/mem_dep_unit.hh @@ -68,7 +68,7 @@ struct SNHash } }; -struct O3CPUParams; +struct BaseO3CPUParams; namespace o3 { @@ -97,7 +97,7 @@ class MemDepUnit MemDepUnit(); /** Constructs a MemDepUnit with given parameters. */ - MemDepUnit(const O3CPUParams ¶ms); + MemDepUnit(const BaseO3CPUParams ¶ms); /** Frees up any memory allocated. */ ~MemDepUnit(); @@ -106,7 +106,7 @@ class MemDepUnit std::string name() const { return _name; } /** Initializes the unit with parameters and a thread id. */ - void init(const O3CPUParams ¶ms, ThreadID tid, CPU *cpu); + void init(const BaseO3CPUParams ¶ms, ThreadID tid, CPU *cpu); /** Determine if we are drained. */ bool isDrained() const; diff --git a/src/cpu/o3/probe/SConscript b/src/cpu/o3/probe/SConscript index bd06b62c1c..d7098ad925 100644 --- a/src/cpu/o3/probe/SConscript +++ b/src/cpu/o3/probe/SConscript @@ -37,7 +37,7 @@ Import('*') -if 'O3CPU' in env['CPU_MODELS']: +if env['TARGET_ISA'] != 'null': SimObject('SimpleTrace.py', sim_objects=['SimpleTrace']) Source('simple_trace.cc') DebugFlag('SimpleTrace') diff --git a/src/cpu/o3/rename.cc b/src/cpu/o3/rename.cc index a3f8700f46..f198870cf2 100644 --- a/src/cpu/o3/rename.cc +++ b/src/cpu/o3/rename.cc @@ -50,7 +50,7 @@ #include "debug/Activity.hh" #include "debug/O3PipeView.hh" #include "debug/Rename.hh" -#include "params/O3CPU.hh" +#include "params/BaseO3CPU.hh" namespace gem5 { @@ -58,7 +58,7 @@ namespace gem5 namespace o3 { -Rename::Rename(CPU *_cpu, const O3CPUParams ¶ms) +Rename::Rename(CPU *_cpu, const BaseO3CPUParams ¶ms) : cpu(_cpu), iewToRenameDelay(params.iewToRenameDelay), decodeToRenameDelay(params.decodeToRenameDelay), diff --git a/src/cpu/o3/rename.hh b/src/cpu/o3/rename.hh index 0204109480..0b42b6eaa0 100644 --- a/src/cpu/o3/rename.hh +++ b/src/cpu/o3/rename.hh @@ -58,7 +58,7 @@ namespace gem5 { -struct O3CPUParams; +struct BaseO3CPUParams; namespace o3 { @@ -125,7 +125,7 @@ class Rename public: /** Rename constructor. */ - Rename(CPU *_cpu, const O3CPUParams ¶ms); + Rename(CPU *_cpu, const BaseO3CPUParams ¶ms); /** Returns the name of rename. */ std::string name() const; diff --git a/src/cpu/o3/rob.cc b/src/cpu/o3/rob.cc index 9e42651f42..5d0fac9a60 100644 --- a/src/cpu/o3/rob.cc +++ b/src/cpu/o3/rob.cc @@ -47,7 +47,7 @@ #include "cpu/o3/limits.hh" #include "debug/Fetch.hh" #include "debug/ROB.hh" -#include "params/O3CPU.hh" +#include "params/BaseO3CPU.hh" namespace gem5 { @@ -55,7 +55,7 @@ namespace gem5 namespace o3 { -ROB::ROB(CPU *_cpu, const O3CPUParams ¶ms) +ROB::ROB(CPU *_cpu, const BaseO3CPUParams ¶ms) : robPolicy(params.smtROBPolicy), cpu(_cpu), numEntries(params.numROBEntries), diff --git a/src/cpu/o3/rob.hh b/src/cpu/o3/rob.hh index 3889ef59db..d36db733e1 100644 --- a/src/cpu/o3/rob.hh +++ b/src/cpu/o3/rob.hh @@ -57,7 +57,7 @@ namespace gem5 { -struct O3CPUParams; +struct BaseO3CPUParams; namespace o3 { @@ -95,7 +95,7 @@ class ROB * @param _cpu The cpu object pointer. * @param params The cpu params including several ROB-specific parameters. */ - ROB(CPU *_cpu, const O3CPUParams ¶ms); + ROB(CPU *_cpu, const BaseO3CPUParams ¶ms); std::string name() const; diff --git a/src/cpu/simple/AtomicSimpleCPU.py b/src/cpu/simple/BaseAtomicSimpleCPU.py similarity index 97% rename from src/cpu/simple/AtomicSimpleCPU.py rename to src/cpu/simple/BaseAtomicSimpleCPU.py index 8dc0a5b1a0..ba3b8121f1 100644 --- a/src/cpu/simple/AtomicSimpleCPU.py +++ b/src/cpu/simple/BaseAtomicSimpleCPU.py @@ -40,12 +40,12 @@ from m5.params import * from m5.objects.BaseSimpleCPU import BaseSimpleCPU from m5.objects.SimPoint import SimPoint -class AtomicSimpleCPU(BaseSimpleCPU): +class BaseAtomicSimpleCPU(BaseSimpleCPU): """Simple CPU model executing a configurable number of instructions per cycle. This model uses the simplified 'atomic' memory mode.""" - type = 'AtomicSimpleCPU' + type = 'BaseAtomicSimpleCPU' cxx_header = "cpu/simple/atomic.hh" cxx_class = 'gem5::AtomicSimpleCPU' diff --git a/src/cpu/simple/NonCachingSimpleCPU.py b/src/cpu/simple/BaseNonCachingSimpleCPU.py similarity index 94% rename from src/cpu/simple/NonCachingSimpleCPU.py rename to src/cpu/simple/BaseNonCachingSimpleCPU.py index e01905a9ae..f5cf1c7a75 100644 --- a/src/cpu/simple/NonCachingSimpleCPU.py +++ b/src/cpu/simple/BaseNonCachingSimpleCPU.py @@ -34,9 +34,9 @@ # OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. from m5.params import * -from m5.objects.AtomicSimpleCPU import AtomicSimpleCPU +from m5.objects.BaseAtomicSimpleCPU import BaseAtomicSimpleCPU -class NonCachingSimpleCPU(AtomicSimpleCPU): +class BaseNonCachingSimpleCPU(BaseAtomicSimpleCPU): """Simple CPU model based on the atomic CPU. Unlike the atomic CPU, this model causes the memory system to bypass caches and is therefore slightly faster in some cases. However, its main purpose @@ -45,7 +45,7 @@ class NonCachingSimpleCPU(AtomicSimpleCPU): """ - type = 'NonCachingSimpleCPU' + type = 'BaseNonCachingSimpleCPU' cxx_header = "cpu/simple/noncaching.hh" cxx_class = 'gem5::NonCachingSimpleCPU' diff --git a/src/cpu/simple/BaseSimpleCPU.py b/src/cpu/simple/BaseSimpleCPU.py index 64444e4137..67ba739767 100644 --- a/src/cpu/simple/BaseSimpleCPU.py +++ b/src/cpu/simple/BaseSimpleCPU.py @@ -37,16 +37,4 @@ class BaseSimpleCPU(BaseCPU): cxx_header = "cpu/simple/base.hh" cxx_class = 'gem5::BaseSimpleCPU' - def addCheckerCpu(self): - if buildEnv['TARGET_ISA'] in ['arm']: - from m5.objects.ArmTLB import ArmMMU - - self.checker = DummyChecker(workload = self.workload) - self.checker.mmu = ArmMMU() - self.checker.mmu.itb.size = self.mmu.itb.size - self.checker.mmu.dtb.size = self.mmu.dtb.size - else: - print("ERROR: Checker only supported under ARM ISA!") - exit(1) - branchPred = Param.BranchPredictor(NULL, "Branch Predictor") diff --git a/src/cpu/simple/TimingSimpleCPU.py b/src/cpu/simple/BaseTimingSimpleCPU.py similarity index 96% rename from src/cpu/simple/TimingSimpleCPU.py rename to src/cpu/simple/BaseTimingSimpleCPU.py index f670cc4c8e..1f317a87be 100644 --- a/src/cpu/simple/TimingSimpleCPU.py +++ b/src/cpu/simple/BaseTimingSimpleCPU.py @@ -28,8 +28,8 @@ from m5.params import * from m5.objects.BaseSimpleCPU import BaseSimpleCPU -class TimingSimpleCPU(BaseSimpleCPU): - type = 'TimingSimpleCPU' +class BaseTimingSimpleCPU(BaseSimpleCPU): + type = 'BaseTimingSimpleCPU' cxx_header = "cpu/simple/timing.hh" cxx_class = 'gem5::TimingSimpleCPU' diff --git a/src/cpu/simple/SConscript b/src/cpu/simple/SConscript index b953d1f852..5a66e8da6c 100644 --- a/src/cpu/simple/SConscript +++ b/src/cpu/simple/SConscript @@ -28,27 +28,21 @@ Import('*') -need_simple_base = False -if 'AtomicSimpleCPU' in env['CPU_MODELS']: - need_simple_base = True - SimObject('AtomicSimpleCPU.py', sim_objects=['AtomicSimpleCPU']) +if env['TARGET_ISA'] != 'null': + SimObject('BaseAtomicSimpleCPU.py', sim_objects=['BaseAtomicSimpleCPU']) Source('atomic.cc') # The NonCachingSimpleCPU is really an atomic CPU in # disguise. It's therefore always enabled when the atomic CPU is # enabled. - SimObject('NonCachingSimpleCPU.py', sim_objects=['NonCachingSimpleCPU']) + SimObject('BaseNonCachingSimpleCPU.py', + sim_objects=['BaseNonCachingSimpleCPU']) Source('noncaching.cc') -if 'TimingSimpleCPU' in env['CPU_MODELS']: - need_simple_base = True - SimObject('TimingSimpleCPU.py', sim_objects=['TimingSimpleCPU']) + SimObject('BaseTimingSimpleCPU.py', sim_objects=['BaseTimingSimpleCPU']) Source('timing.cc') -if 'AtomicSimpleCPU' in env['CPU_MODELS'] or \ - 'TimingSimpleCPU' in env['CPU_MODELS']: DebugFlag('SimpleCPU') -if need_simple_base: Source('base.cc') SimObject('BaseSimpleCPU.py', sim_objects=['BaseSimpleCPU']) diff --git a/src/cpu/simple/atomic.cc b/src/cpu/simple/atomic.cc index d9e36758f1..9cf7a294b9 100644 --- a/src/cpu/simple/atomic.cc +++ b/src/cpu/simple/atomic.cc @@ -52,7 +52,7 @@ #include "mem/packet.hh" #include "mem/packet_access.hh" #include "mem/physical.hh" -#include "params/AtomicSimpleCPU.hh" +#include "params/BaseAtomicSimpleCPU.hh" #include "sim/faults.hh" #include "sim/full_system.hh" #include "sim/system.hh" @@ -72,7 +72,7 @@ AtomicSimpleCPU::init() data_amo_req->setContext(cid); } -AtomicSimpleCPU::AtomicSimpleCPU(const AtomicSimpleCPUParams &p) +AtomicSimpleCPU::AtomicSimpleCPU(const BaseAtomicSimpleCPUParams &p) : BaseSimpleCPU(p), tickEvent([this]{ tick(); }, "AtomicSimpleCPU tick", false, Event::CPU_Tick_Pri), diff --git a/src/cpu/simple/atomic.hh b/src/cpu/simple/atomic.hh index aacd0dc033..c0d0f1d0bc 100644 --- a/src/cpu/simple/atomic.hh +++ b/src/cpu/simple/atomic.hh @@ -44,7 +44,7 @@ #include "cpu/simple/base.hh" #include "cpu/simple/exec_context.hh" #include "mem/request.hh" -#include "params/AtomicSimpleCPU.hh" +#include "params/BaseAtomicSimpleCPU.hh" #include "sim/probe/probe.hh" namespace gem5 @@ -54,7 +54,7 @@ class AtomicSimpleCPU : public BaseSimpleCPU { public: - AtomicSimpleCPU(const AtomicSimpleCPUParams ¶ms); + AtomicSimpleCPU(const BaseAtomicSimpleCPUParams ¶ms); virtual ~AtomicSimpleCPU(); void init() override; diff --git a/src/cpu/simple/noncaching.cc b/src/cpu/simple/noncaching.cc index 6458beeb28..424a496fe9 100644 --- a/src/cpu/simple/noncaching.cc +++ b/src/cpu/simple/noncaching.cc @@ -44,7 +44,8 @@ namespace gem5 { -NonCachingSimpleCPU::NonCachingSimpleCPU(const NonCachingSimpleCPUParams &p) +NonCachingSimpleCPU::NonCachingSimpleCPU( + const BaseNonCachingSimpleCPUParams &p) : AtomicSimpleCPU(p) { assert(p.numThreads == 1); diff --git a/src/cpu/simple/noncaching.hh b/src/cpu/simple/noncaching.hh index 289f482d43..5dea9c6498 100644 --- a/src/cpu/simple/noncaching.hh +++ b/src/cpu/simple/noncaching.hh @@ -41,7 +41,7 @@ #include "base/addr_range_map.hh" #include "cpu/simple/atomic.hh" #include "mem/backdoor.hh" -#include "params/NonCachingSimpleCPU.hh" +#include "params/BaseNonCachingSimpleCPU.hh" namespace gem5 { @@ -53,7 +53,7 @@ namespace gem5 class NonCachingSimpleCPU : public AtomicSimpleCPU { public: - NonCachingSimpleCPU(const NonCachingSimpleCPUParams &p); + NonCachingSimpleCPU(const BaseNonCachingSimpleCPUParams &p); void verifyMemoryMode() const override; diff --git a/src/cpu/simple/probes/SConscript b/src/cpu/simple/probes/SConscript index eae6a4581e..1c8abdb58e 100644 --- a/src/cpu/simple/probes/SConscript +++ b/src/cpu/simple/probes/SConscript @@ -28,6 +28,6 @@ Import('*') -if 'AtomicSimpleCPU' in env['CPU_MODELS']: +if env['TARGET_ISA'] != 'null': SimObject('SimPoint.py', sim_objects=['SimPoint']) Source('simpoint.cc') diff --git a/src/cpu/simple/timing.cc b/src/cpu/simple/timing.cc index c7e63efa84..d562c1710f 100644 --- a/src/cpu/simple/timing.cc +++ b/src/cpu/simple/timing.cc @@ -53,7 +53,7 @@ #include "debug/SimpleCPU.hh" #include "mem/packet.hh" #include "mem/packet_access.hh" -#include "params/TimingSimpleCPU.hh" +#include "params/BaseTimingSimpleCPU.hh" #include "sim/faults.hh" #include "sim/full_system.hh" #include "sim/system.hh" @@ -74,7 +74,7 @@ TimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t) cpu->schedule(this, t); } -TimingSimpleCPU::TimingSimpleCPU(const TimingSimpleCPUParams &p) +TimingSimpleCPU::TimingSimpleCPU(const BaseTimingSimpleCPUParams &p) : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this), dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0), fetchEvent([this]{ fetch(); }, name()) diff --git a/src/cpu/simple/timing.hh b/src/cpu/simple/timing.hh index b2cc4e7ffd..b211ab14b4 100644 --- a/src/cpu/simple/timing.hh +++ b/src/cpu/simple/timing.hh @@ -45,7 +45,7 @@ #include "cpu/simple/base.hh" #include "cpu/simple/exec_context.hh" #include "cpu/translation.hh" -#include "params/TimingSimpleCPU.hh" +#include "params/BaseTimingSimpleCPU.hh" namespace gem5 { @@ -54,7 +54,7 @@ class TimingSimpleCPU : public BaseSimpleCPU { public: - TimingSimpleCPU(const TimingSimpleCPUParams ¶ms); + TimingSimpleCPU(const BaseTimingSimpleCPUParams ¶ms); virtual ~TimingSimpleCPU(); void init() override; diff --git a/src/cpu/testers/memtest/SConscript b/src/cpu/testers/memtest/SConscript index 51e443bd07..766739d609 100644 --- a/src/cpu/testers/memtest/SConscript +++ b/src/cpu/testers/memtest/SConscript @@ -28,7 +28,6 @@ Import('*') -#if 'O3CPU' in env['CPU_MODELS']: SimObject('MemTest.py', sim_objects=['MemTest']) Source('memtest.cc')