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cpu,arch: Put the name of the RegClass into the RegClass.

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Move the name of the RegClass out of constants which belong to the
RegId, and instead store them in the RegClass instances.

Change-Id: I1ddd4bc8467d5e3f178db7a11c8f8052f43fd7ec
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/50251
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
This commit is contained in:
Gabe Black
2021-09-11 00:17:13 -07:00
parent 7b1f05a34c
commit cc4380b0d6
28 changed files with 86 additions and 76 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/arch/arm/isa.cc
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@@ -74,7 +74,7 @@ namespace
{
/* Not applicable to ARM */
RegClass floatRegClass(FloatRegClass, 0, debug::FloatRegs);
RegClass floatRegClass(FloatRegClass, FloatRegClassName, 0, debug::FloatRegs);
} // anonymous namespace

4
src/arch/arm/regs/cc.hh
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@@ -63,8 +63,8 @@ enum : RegIndex
} // namespace cc_reg
inline constexpr RegClass ccRegClass(CCRegClass, cc_reg::NumRegs,
debug::CCRegs);
inline constexpr RegClass ccRegClass(CCRegClass, CCRegClassName,
cc_reg::NumRegs, debug::CCRegs);
namespace cc_reg
{

4
src/arch/arm/regs/int.hh
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@@ -163,8 +163,8 @@ enum : RegIndex
} // namespace int_reg
inline constexpr RegClass intRegClass(IntRegClass, int_reg::NumRegs,
debug::IntRegs);
inline constexpr RegClass intRegClass(IntRegClass, IntRegClassName,
int_reg::NumRegs, debug::IntRegs);
namespace int_reg
{

3
src/arch/arm/regs/misc.hh
View File

@@ -2724,7 +2724,8 @@ namespace ArmISA
static inline MiscRegClassOps miscRegClassOps;
inline constexpr RegClass miscRegClass =
RegClass(MiscRegClass, NUM_MISCREGS, debug::MiscRegs).
RegClass(MiscRegClass, MiscRegClassName, NUM_MISCREGS,
debug::MiscRegs).
ops(miscRegClassOps);
// This mask selects bits of the CPSR that actually go in the CondCodes

8
src/arch/arm/regs/vec.hh
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@@ -99,14 +99,16 @@ static inline TypedRegClassOps<ArmISA::VecRegContainer> vecRegClassOps;
static inline TypedRegClassOps<ArmISA::VecPredRegContainer> vecPredRegClassOps;
inline constexpr RegClass vecRegClass =
RegClass(VecRegClass, NumVecRegs, debug::VecRegs).
RegClass(VecRegClass, VecRegClassName, NumVecRegs, debug::VecRegs).
ops(vecRegClassOps).
regType<VecRegContainer>();
inline constexpr RegClass vecElemClass =
RegClass(VecElemClass, NumVecRegs * NumVecElemPerVecReg, debug::VecRegs).
RegClass(VecElemClass, VecElemClassName, NumVecRegs * NumVecElemPerVecReg,
debug::VecRegs).
ops(vecRegElemClassOps);
inline constexpr RegClass vecPredRegClass =
RegClass(VecPredRegClass, NumVecPredRegs, debug::VecPredRegs).
RegClass(VecPredRegClass, VecPredRegClassName, NumVecPredRegs,
debug::VecPredRegs).
ops(vecPredRegClassOps).
regType<VecPredRegContainer>();

11
src/arch/mips/isa.cc
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@@ -98,10 +98,13 @@ namespace
{
/* Not applicable to MIPS. */
constexpr RegClass vecRegClass(VecRegClass, 1, debug::IntRegs);
constexpr RegClass vecElemClass(VecElemClass, 2, debug::IntRegs);
constexpr RegClass vecPredRegClass(VecPredRegClass, 1, debug::IntRegs);
constexpr RegClass ccRegClass(CCRegClass, 0, debug::IntRegs);
constexpr RegClass vecRegClass(VecRegClass, VecRegClassName, 1,
debug::IntRegs);
constexpr RegClass vecElemClass(VecElemClass, VecElemClassName, 2,
debug::IntRegs);
constexpr RegClass vecPredRegClass(VecPredRegClass, VecPredRegClassName, 1,
debug::IntRegs);
constexpr RegClass ccRegClass(CCRegClass, CCRegClassName, 0, debug::IntRegs);
} // anonymous namespace

4
src/arch/mips/regs/float.hh
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@@ -89,8 +89,8 @@ enum : RegIndex
} // namespace float_reg
inline constexpr RegClass floatRegClass(FloatRegClass, float_reg::NumRegs,
debug::FloatRegs);
inline constexpr RegClass floatRegClass(FloatRegClass, FloatRegClassName,
float_reg::NumRegs, debug::FloatRegs);
namespace float_reg
{

4
src/arch/mips/regs/int.hh
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@@ -119,8 +119,8 @@ enum : RegIndex
} // namespace int_reg
inline constexpr RegClass intRegClass(IntRegClass, int_reg::NumRegs,
debug::IntRegs);
inline constexpr RegClass intRegClass(IntRegClass, IntRegClassName,
int_reg::NumRegs, debug::IntRegs);
namespace int_reg
{

4
src/arch/mips/regs/misc.hh
View File

@@ -200,8 +200,8 @@ enum : RegIndex
} // namespace misc_reg
inline constexpr RegClass miscRegClass(MiscRegClass, misc_reg::NumRegs,
debug::MiscRegs);
inline constexpr RegClass miscRegClass(MiscRegClass, MiscRegClassName,
misc_reg::NumRegs, debug::MiscRegs);
} // namespace MipsISA
} // namespace gem5

9
src/arch/power/isa.cc
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@@ -52,10 +52,11 @@ namespace PowerISA
namespace
{
RegClass vecRegClass(VecRegClass, 1, debug::IntRegs);
RegClass vecElemClass(VecElemClass, 2, debug::IntRegs);
RegClass vecPredRegClass(VecPredRegClass, 1, debug::IntRegs);
RegClass ccRegClass(CCRegClass, 0, debug::IntRegs);
RegClass vecRegClass(VecRegClass, VecRegClassName, 1, debug::IntRegs);
RegClass vecElemClass(VecElemClass, VecElemClassName, 2, debug::IntRegs);
RegClass vecPredRegClass(VecPredRegClass, VecPredRegClassName, 1,
debug::IntRegs);
RegClass ccRegClass(CCRegClass, CCRegClassName, 0, debug::IntRegs);
} // anonymous namespace

4
src/arch/power/regs/float.hh
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@@ -46,8 +46,8 @@ const int NumRegs = NumArchRegs;
} // namespace float_reg
inline constexpr RegClass floatRegClass(FloatRegClass, float_reg::NumRegs,
debug::FloatRegs);
inline constexpr RegClass floatRegClass(FloatRegClass, FloatRegClassName,
float_reg::NumRegs, debug::FloatRegs);
} // namespace PowerISA
} // namespace gem5

4
src/arch/power/regs/int.hh
View File

@@ -95,8 +95,8 @@ enum : RegIndex
} // namespace int_reg
inline constexpr RegClass intRegClass(IntRegClass, int_reg::NumRegs,
debug::IntRegs);
inline constexpr RegClass intRegClass(IntRegClass, IntRegClassName,
int_reg::NumRegs, debug::IntRegs);
namespace int_reg
{

4
src/arch/power/regs/misc.hh
View File

@@ -48,8 +48,8 @@ enum MiscRegIndex
const char * const miscRegName[NUM_MISCREGS] = {
};
inline constexpr RegClass miscRegClass(MiscRegClass, NUM_MISCREGS,
debug::MiscRegs);
inline constexpr RegClass miscRegClass(MiscRegClass, MiscRegClassName,
NUM_MISCREGS, debug::MiscRegs);
BitUnion32(Cr)
SubBitUnion(cr0, 31, 28)

9
src/arch/riscv/isa.cc
View File

@@ -195,10 +195,11 @@ namespace
{
/* Not applicable to RISCV */
RegClass vecRegClass(VecRegClass, 1, debug::IntRegs);
RegClass vecElemClass(VecElemClass, 2, debug::IntRegs);
RegClass vecPredRegClass(VecPredRegClass, 1, debug::IntRegs);
RegClass ccRegClass(CCRegClass, 0, debug::IntRegs);
RegClass vecRegClass(VecRegClass, VecRegClassName, 1, debug::IntRegs);
RegClass vecElemClass(VecElemClass, VecElemClassName, 2, debug::IntRegs);
RegClass vecPredRegClass(VecPredRegClass, VecPredRegClassName, 1,
debug::IntRegs);
RegClass ccRegClass(CCRegClass, CCRegClassName, 0, debug::IntRegs);
} // anonymous namespace

4
src/arch/riscv/regs/float.hh
View File

@@ -154,8 +154,8 @@ enum : RegIndex
} // namespace float_reg
inline constexpr RegClass floatRegClass(FloatRegClass, float_reg::NumRegs,
debug::FloatRegs);
inline constexpr RegClass floatRegClass(FloatRegClass, FloatRegClassName,
float_reg::NumRegs, debug::FloatRegs);
namespace float_reg
{

4
src/arch/riscv/regs/int.hh
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@@ -81,8 +81,8 @@ enum : RegIndex
} // namespace int_reg
inline constexpr RegClass intRegClass(IntRegClass, int_reg::NumRegs,
debug::IntRegs);
inline constexpr RegClass intRegClass(IntRegClass, IntRegClassName,
int_reg::NumRegs, debug::IntRegs);
namespace int_reg
{

4
src/arch/riscv/regs/misc.hh
View File

@@ -202,8 +202,8 @@ enum MiscRegIndex
NUM_MISCREGS
};
inline constexpr RegClass miscRegClass(MiscRegClass, NUM_MISCREGS,
debug::MiscRegs);
inline constexpr RegClass miscRegClass(MiscRegClass, MiscRegClassName,
NUM_MISCREGS, debug::MiscRegs);
enum CSRIndex
{

9
src/arch/sparc/isa.cc
View File

@@ -69,10 +69,11 @@ namespace
{
/* Not applicable for SPARC */
RegClass vecRegClass(VecRegClass, 1, debug::IntRegs);
RegClass vecElemClass(VecElemClass, 2, debug::IntRegs);
RegClass vecPredRegClass(VecPredRegClass, 1, debug::IntRegs);
RegClass ccRegClass(CCRegClass, 0, debug::IntRegs);
RegClass vecRegClass(VecRegClass, VecRegClassName, 1, debug::IntRegs);
RegClass vecElemClass(VecElemClass, VecElemClassName, 2, debug::IntRegs);
RegClass vecPredRegClass(VecPredRegClass, VecPredRegClassName, 1,
debug::IntRegs);
RegClass ccRegClass(CCRegClass, CCRegClassName, 0, debug::IntRegs);
} // anonymous namespace

4
src/arch/sparc/regs/float.hh
View File

@@ -46,8 +46,8 @@ const int NumArchRegs = NumRegs;
} // namespace float_reg
inline constexpr RegClass floatRegClass(FloatRegClass, float_reg::NumRegs,
debug::FloatRegs);
inline constexpr RegClass floatRegClass(FloatRegClass, FloatRegClassName,
float_reg::NumRegs, debug::FloatRegs);
} // namespace SparcISA
} // namespace gem5

4
src/arch/sparc/regs/int.hh
View File

@@ -68,8 +68,8 @@ const int NumRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroRegs;
} // namespace int_reg
inline constexpr RegClass intRegClass(IntRegClass, int_reg::NumRegs,
debug::IntRegs);
inline constexpr RegClass intRegClass(IntRegClass, IntRegClassName,
int_reg::NumRegs, debug::IntRegs);
namespace int_reg
{

4
src/arch/sparc/regs/misc.hh
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@@ -174,8 +174,8 @@ struct STS
const int NumMiscRegs = MISCREG_NUMMISCREGS;
inline constexpr RegClass miscRegClass(MiscRegClass, NumMiscRegs,
debug::MiscRegs);
inline constexpr RegClass miscRegClass(MiscRegClass, MiscRegClassName,
NumMiscRegs, debug::MiscRegs);
} // namespace SparcISA
} // namespace gem5

7
src/arch/x86/isa.cc
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@@ -142,9 +142,10 @@ namespace
{
/* Not applicable to X86 */
RegClass vecRegClass(VecRegClass, 1, debug::IntRegs);
RegClass vecElemClass(VecElemClass, 2, debug::IntRegs);
RegClass vecPredRegClass(VecPredRegClass, 1, debug::IntRegs);
RegClass vecRegClass(VecRegClass, VecRegClassName, 1, debug::IntRegs);
RegClass vecElemClass(VecElemClass, VecElemClassName, 2, debug::IntRegs);
RegClass vecPredRegClass(VecPredRegClass, VecPredRegClassName, 1,
debug::IntRegs);
} // anonymous namespace

4
src/arch/x86/regs/ccr.hh
View File

@@ -61,8 +61,8 @@ enum : RegIndex
} // namespace cc_reg
inline constexpr RegClass ccRegClass(CCRegClass, cc_reg::NumRegs,
debug::CCRegs);
inline constexpr RegClass ccRegClass(CCRegClass, CCRegClassName,
cc_reg::NumRegs, debug::CCRegs);
namespace cc_reg
{

4
src/arch/x86/regs/float.hh
View File

@@ -121,8 +121,8 @@ enum FloatRegIndex
} // namespace float_reg
inline constexpr RegClass floatRegClass(FloatRegClass, float_reg::NumRegs,
debug::FloatRegs);
inline constexpr RegClass floatRegClass(FloatRegClass, FloatRegClassName,
float_reg::NumRegs, debug::FloatRegs);
namespace float_reg
{

4
src/arch/x86/regs/int.hh
View File

@@ -102,8 +102,8 @@ enum : RegIndex
} // namespace int_reg
inline constexpr RegClass intRegClass(IntRegClass, int_reg::NumRegs,
debug::IntRegs);
inline constexpr RegClass intRegClass(IntRegClass, IntRegClassName,
int_reg::NumRegs, debug::IntRegs);
namespace int_reg
{

4
src/arch/x86/regs/misc.hh
View File

@@ -538,8 +538,8 @@ segAttr(int index)
} // namespace misc_reg
inline constexpr RegClass miscRegClass(MiscRegClass, misc_reg::NumRegs,
debug::MiscRegs);
inline constexpr RegClass miscRegClass(MiscRegClass, MiscRegClassName,
misc_reg::NumRegs, debug::MiscRegs);
/**
* A type to describe the condition code bits of the RFLAGS register,

10
src/cpu/reg_class.cc
View File

@@ -71,14 +71,4 @@ RegClassOps::valString(const void *val, size_t size) const
return printByteBuf(val, size, ByteOrder::big);
}
const char *RegId::regClassStrings[] = {
"IntRegClass",
"FloatRegClass",
"VecRegClass",
"VecElemClass",
"VecPredRegClass",
"CCRegClass",
"MiscRegClass"
};
} // namespace gem5

22
src/cpu/reg_class.hh
View File

@@ -69,6 +69,15 @@ enum RegClassType
InvalidRegClass = -1
};
// "Standard" register class names. Using these is encouraged but optional.
inline constexpr char IntRegClassName[] = "integer";
inline constexpr char FloatRegClassName[] = "floating_point";
inline constexpr char VecRegClassName[] = "vector";
inline constexpr char VecElemClassName[] = "vector_element";
inline constexpr char VecPredRegClassName[] = "vector_predicate";
inline constexpr char CCRegClassName[] = "condition_code";
inline constexpr char MiscRegClassName[] = "miscellaneous";
class RegId;
class RegClassOps
@@ -86,6 +95,7 @@ class RegClass
{
private:
RegClassType _type;
const char *_name;
size_t _numRegs;
size_t _regBytes = sizeof(RegVal);
@@ -99,9 +109,9 @@ class RegClass
const debug::Flag &debugFlag;
public:
constexpr RegClass(RegClassType type, size_t num_regs,
const debug::Flag &debug_flag) :
_type(type), _numRegs(num_regs), debugFlag(debug_flag)
constexpr RegClass(RegClassType type, const char *new_name,
size_t num_regs, const debug::Flag &debug_flag) :
_type(type), _name(new_name), _numRegs(num_regs), debugFlag(debug_flag)
{}
constexpr RegClass
@@ -123,6 +133,7 @@ class RegClass
}
constexpr RegClassType type() const { return _type; }
constexpr const char *name() const { return _name; }
constexpr size_t numRegs() const { return _numRegs; }
constexpr size_t regBytes() const { return _regBytes; }
constexpr size_t regShift() const { return _regShift; }
@@ -144,7 +155,7 @@ class RegClass
};
inline constexpr RegClass
invalidRegClass(InvalidRegClass, 0, debug::InvalidReg);
invalidRegClass(InvalidRegClass, "invalid", 0, debug::InvalidReg);
/** Register ID: describe an architectural register with its class and index.
* This structure is used instead of just the register index to disambiguate
@@ -154,7 +165,6 @@ inline constexpr RegClass
class RegId
{
protected:
static const char* regClassStrings[];
const RegClass *_regClass = nullptr;
RegIndex regIdx;
int numPinnedWrites;
@@ -223,7 +233,7 @@ class RegId
constexpr const char*
className() const
{
return regClassStrings[classValue()];
return _regClass->name();
}
int getNumPinnedWrites() const { return numPinnedWrites; }