diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 288543c606..5f128f883c 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -74,7 +74,7 @@ namespace { /* Not applicable to ARM */ -RegClass floatRegClass(FloatRegClass, 0, debug::FloatRegs); +RegClass floatRegClass(FloatRegClass, FloatRegClassName, 0, debug::FloatRegs); } // anonymous namespace diff --git a/src/arch/arm/regs/cc.hh b/src/arch/arm/regs/cc.hh index e3792cb89f..ba7552799a 100644 --- a/src/arch/arm/regs/cc.hh +++ b/src/arch/arm/regs/cc.hh @@ -63,8 +63,8 @@ enum : RegIndex } // namespace cc_reg -inline constexpr RegClass ccRegClass(CCRegClass, cc_reg::NumRegs, - debug::CCRegs); +inline constexpr RegClass ccRegClass(CCRegClass, CCRegClassName, + cc_reg::NumRegs, debug::CCRegs); namespace cc_reg { diff --git a/src/arch/arm/regs/int.hh b/src/arch/arm/regs/int.hh index 61bdc1d082..1b414493ee 100644 --- a/src/arch/arm/regs/int.hh +++ b/src/arch/arm/regs/int.hh @@ -163,8 +163,8 @@ enum : RegIndex } // namespace int_reg -inline constexpr RegClass intRegClass(IntRegClass, int_reg::NumRegs, - debug::IntRegs); +inline constexpr RegClass intRegClass(IntRegClass, IntRegClassName, + int_reg::NumRegs, debug::IntRegs); namespace int_reg { diff --git a/src/arch/arm/regs/misc.hh b/src/arch/arm/regs/misc.hh index 3cd675dc1f..0b61eec2d6 100644 --- a/src/arch/arm/regs/misc.hh +++ b/src/arch/arm/regs/misc.hh @@ -2724,7 +2724,8 @@ namespace ArmISA static inline MiscRegClassOps miscRegClassOps; inline constexpr RegClass miscRegClass = - RegClass(MiscRegClass, NUM_MISCREGS, debug::MiscRegs). + RegClass(MiscRegClass, MiscRegClassName, NUM_MISCREGS, + debug::MiscRegs). ops(miscRegClassOps); // This mask selects bits of the CPSR that actually go in the CondCodes diff --git a/src/arch/arm/regs/vec.hh b/src/arch/arm/regs/vec.hh index 45eac30c4b..00ab87fbcb 100644 --- a/src/arch/arm/regs/vec.hh +++ b/src/arch/arm/regs/vec.hh @@ -99,14 +99,16 @@ static inline TypedRegClassOps vecRegClassOps; static inline TypedRegClassOps vecPredRegClassOps; inline constexpr RegClass vecRegClass = - RegClass(VecRegClass, NumVecRegs, debug::VecRegs). + RegClass(VecRegClass, VecRegClassName, NumVecRegs, debug::VecRegs). ops(vecRegClassOps). regType(); inline constexpr RegClass vecElemClass = - RegClass(VecElemClass, NumVecRegs * NumVecElemPerVecReg, debug::VecRegs). + RegClass(VecElemClass, VecElemClassName, NumVecRegs * NumVecElemPerVecReg, + debug::VecRegs). ops(vecRegElemClassOps); inline constexpr RegClass vecPredRegClass = - RegClass(VecPredRegClass, NumVecPredRegs, debug::VecPredRegs). + RegClass(VecPredRegClass, VecPredRegClassName, NumVecPredRegs, + debug::VecPredRegs). ops(vecPredRegClassOps). regType(); diff --git a/src/arch/mips/isa.cc b/src/arch/mips/isa.cc index 7a95e49407..0fee5f8654 100644 --- a/src/arch/mips/isa.cc +++ b/src/arch/mips/isa.cc @@ -98,10 +98,13 @@ namespace { /* Not applicable to MIPS. */ -constexpr RegClass vecRegClass(VecRegClass, 1, debug::IntRegs); -constexpr RegClass vecElemClass(VecElemClass, 2, debug::IntRegs); -constexpr RegClass vecPredRegClass(VecPredRegClass, 1, debug::IntRegs); -constexpr RegClass ccRegClass(CCRegClass, 0, debug::IntRegs); +constexpr RegClass vecRegClass(VecRegClass, VecRegClassName, 1, + debug::IntRegs); +constexpr RegClass vecElemClass(VecElemClass, VecElemClassName, 2, + debug::IntRegs); +constexpr RegClass vecPredRegClass(VecPredRegClass, VecPredRegClassName, 1, + debug::IntRegs); +constexpr RegClass ccRegClass(CCRegClass, CCRegClassName, 0, debug::IntRegs); } // anonymous namespace diff --git a/src/arch/mips/regs/float.hh b/src/arch/mips/regs/float.hh index a61e61b645..7c24e0704e 100644 --- a/src/arch/mips/regs/float.hh +++ b/src/arch/mips/regs/float.hh @@ -89,8 +89,8 @@ enum : RegIndex } // namespace float_reg -inline constexpr RegClass floatRegClass(FloatRegClass, float_reg::NumRegs, - debug::FloatRegs); +inline constexpr RegClass floatRegClass(FloatRegClass, FloatRegClassName, + float_reg::NumRegs, debug::FloatRegs); namespace float_reg { diff --git a/src/arch/mips/regs/int.hh b/src/arch/mips/regs/int.hh index 1981d0a17a..f891096d78 100644 --- a/src/arch/mips/regs/int.hh +++ b/src/arch/mips/regs/int.hh @@ -119,8 +119,8 @@ enum : RegIndex } // namespace int_reg -inline constexpr RegClass intRegClass(IntRegClass, int_reg::NumRegs, - debug::IntRegs); +inline constexpr RegClass intRegClass(IntRegClass, IntRegClassName, + int_reg::NumRegs, debug::IntRegs); namespace int_reg { diff --git a/src/arch/mips/regs/misc.hh b/src/arch/mips/regs/misc.hh index 90251d6ae1..0521d85487 100644 --- a/src/arch/mips/regs/misc.hh +++ b/src/arch/mips/regs/misc.hh @@ -200,8 +200,8 @@ enum : RegIndex } // namespace misc_reg -inline constexpr RegClass miscRegClass(MiscRegClass, misc_reg::NumRegs, - debug::MiscRegs); +inline constexpr RegClass miscRegClass(MiscRegClass, MiscRegClassName, + misc_reg::NumRegs, debug::MiscRegs); } // namespace MipsISA } // namespace gem5 diff --git a/src/arch/power/isa.cc b/src/arch/power/isa.cc index 0646c11681..80c984cfc4 100644 --- a/src/arch/power/isa.cc +++ b/src/arch/power/isa.cc @@ -52,10 +52,11 @@ namespace PowerISA namespace { -RegClass vecRegClass(VecRegClass, 1, debug::IntRegs); -RegClass vecElemClass(VecElemClass, 2, debug::IntRegs); -RegClass vecPredRegClass(VecPredRegClass, 1, debug::IntRegs); -RegClass ccRegClass(CCRegClass, 0, debug::IntRegs); +RegClass vecRegClass(VecRegClass, VecRegClassName, 1, debug::IntRegs); +RegClass vecElemClass(VecElemClass, VecElemClassName, 2, debug::IntRegs); +RegClass vecPredRegClass(VecPredRegClass, VecPredRegClassName, 1, + debug::IntRegs); +RegClass ccRegClass(CCRegClass, CCRegClassName, 0, debug::IntRegs); } // anonymous namespace diff --git a/src/arch/power/regs/float.hh b/src/arch/power/regs/float.hh index 11f1aab95c..654460eac9 100644 --- a/src/arch/power/regs/float.hh +++ b/src/arch/power/regs/float.hh @@ -46,8 +46,8 @@ const int NumRegs = NumArchRegs; } // namespace float_reg -inline constexpr RegClass floatRegClass(FloatRegClass, float_reg::NumRegs, - debug::FloatRegs); +inline constexpr RegClass floatRegClass(FloatRegClass, FloatRegClassName, + float_reg::NumRegs, debug::FloatRegs); } // namespace PowerISA } // namespace gem5 diff --git a/src/arch/power/regs/int.hh b/src/arch/power/regs/int.hh index cdd2d6e5e0..6bb95cdc7f 100644 --- a/src/arch/power/regs/int.hh +++ b/src/arch/power/regs/int.hh @@ -95,8 +95,8 @@ enum : RegIndex } // namespace int_reg -inline constexpr RegClass intRegClass(IntRegClass, int_reg::NumRegs, - debug::IntRegs); +inline constexpr RegClass intRegClass(IntRegClass, IntRegClassName, + int_reg::NumRegs, debug::IntRegs); namespace int_reg { diff --git a/src/arch/power/regs/misc.hh b/src/arch/power/regs/misc.hh index 1ab8e4215c..8601697135 100644 --- a/src/arch/power/regs/misc.hh +++ b/src/arch/power/regs/misc.hh @@ -48,8 +48,8 @@ enum MiscRegIndex const char * const miscRegName[NUM_MISCREGS] = { }; -inline constexpr RegClass miscRegClass(MiscRegClass, NUM_MISCREGS, - debug::MiscRegs); +inline constexpr RegClass miscRegClass(MiscRegClass, MiscRegClassName, + NUM_MISCREGS, debug::MiscRegs); BitUnion32(Cr) SubBitUnion(cr0, 31, 28) diff --git a/src/arch/riscv/isa.cc b/src/arch/riscv/isa.cc index f0df13de1c..a5e19164ec 100644 --- a/src/arch/riscv/isa.cc +++ b/src/arch/riscv/isa.cc @@ -195,10 +195,11 @@ namespace { /* Not applicable to RISCV */ -RegClass vecRegClass(VecRegClass, 1, debug::IntRegs); -RegClass vecElemClass(VecElemClass, 2, debug::IntRegs); -RegClass vecPredRegClass(VecPredRegClass, 1, debug::IntRegs); -RegClass ccRegClass(CCRegClass, 0, debug::IntRegs); +RegClass vecRegClass(VecRegClass, VecRegClassName, 1, debug::IntRegs); +RegClass vecElemClass(VecElemClass, VecElemClassName, 2, debug::IntRegs); +RegClass vecPredRegClass(VecPredRegClass, VecPredRegClassName, 1, + debug::IntRegs); +RegClass ccRegClass(CCRegClass, CCRegClassName, 0, debug::IntRegs); } // anonymous namespace diff --git a/src/arch/riscv/regs/float.hh b/src/arch/riscv/regs/float.hh index 701e818711..1654bdb627 100644 --- a/src/arch/riscv/regs/float.hh +++ b/src/arch/riscv/regs/float.hh @@ -154,8 +154,8 @@ enum : RegIndex } // namespace float_reg -inline constexpr RegClass floatRegClass(FloatRegClass, float_reg::NumRegs, - debug::FloatRegs); +inline constexpr RegClass floatRegClass(FloatRegClass, FloatRegClassName, + float_reg::NumRegs, debug::FloatRegs); namespace float_reg { diff --git a/src/arch/riscv/regs/int.hh b/src/arch/riscv/regs/int.hh index 3ca73ac0cc..4ac01c60c1 100644 --- a/src/arch/riscv/regs/int.hh +++ b/src/arch/riscv/regs/int.hh @@ -81,8 +81,8 @@ enum : RegIndex } // namespace int_reg -inline constexpr RegClass intRegClass(IntRegClass, int_reg::NumRegs, - debug::IntRegs); +inline constexpr RegClass intRegClass(IntRegClass, IntRegClassName, + int_reg::NumRegs, debug::IntRegs); namespace int_reg { diff --git a/src/arch/riscv/regs/misc.hh b/src/arch/riscv/regs/misc.hh index b3d92b43cf..e0efe9705c 100644 --- a/src/arch/riscv/regs/misc.hh +++ b/src/arch/riscv/regs/misc.hh @@ -202,8 +202,8 @@ enum MiscRegIndex NUM_MISCREGS }; -inline constexpr RegClass miscRegClass(MiscRegClass, NUM_MISCREGS, - debug::MiscRegs); +inline constexpr RegClass miscRegClass(MiscRegClass, MiscRegClassName, + NUM_MISCREGS, debug::MiscRegs); enum CSRIndex { diff --git a/src/arch/sparc/isa.cc b/src/arch/sparc/isa.cc index 9f2906d71f..1ffd25dcff 100644 --- a/src/arch/sparc/isa.cc +++ b/src/arch/sparc/isa.cc @@ -69,10 +69,11 @@ namespace { /* Not applicable for SPARC */ -RegClass vecRegClass(VecRegClass, 1, debug::IntRegs); -RegClass vecElemClass(VecElemClass, 2, debug::IntRegs); -RegClass vecPredRegClass(VecPredRegClass, 1, debug::IntRegs); -RegClass ccRegClass(CCRegClass, 0, debug::IntRegs); +RegClass vecRegClass(VecRegClass, VecRegClassName, 1, debug::IntRegs); +RegClass vecElemClass(VecElemClass, VecElemClassName, 2, debug::IntRegs); +RegClass vecPredRegClass(VecPredRegClass, VecPredRegClassName, 1, + debug::IntRegs); +RegClass ccRegClass(CCRegClass, CCRegClassName, 0, debug::IntRegs); } // anonymous namespace diff --git a/src/arch/sparc/regs/float.hh b/src/arch/sparc/regs/float.hh index 8398b73e94..64a9de0065 100644 --- a/src/arch/sparc/regs/float.hh +++ b/src/arch/sparc/regs/float.hh @@ -46,8 +46,8 @@ const int NumArchRegs = NumRegs; } // namespace float_reg -inline constexpr RegClass floatRegClass(FloatRegClass, float_reg::NumRegs, - debug::FloatRegs); +inline constexpr RegClass floatRegClass(FloatRegClass, FloatRegClassName, + float_reg::NumRegs, debug::FloatRegs); } // namespace SparcISA } // namespace gem5 diff --git a/src/arch/sparc/regs/int.hh b/src/arch/sparc/regs/int.hh index b1bfcae342..05c5f624b1 100644 --- a/src/arch/sparc/regs/int.hh +++ b/src/arch/sparc/regs/int.hh @@ -68,8 +68,8 @@ const int NumRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroRegs; } // namespace int_reg -inline constexpr RegClass intRegClass(IntRegClass, int_reg::NumRegs, - debug::IntRegs); +inline constexpr RegClass intRegClass(IntRegClass, IntRegClassName, + int_reg::NumRegs, debug::IntRegs); namespace int_reg { diff --git a/src/arch/sparc/regs/misc.hh b/src/arch/sparc/regs/misc.hh index 0f008c3aef..0c2fa18e5a 100644 --- a/src/arch/sparc/regs/misc.hh +++ b/src/arch/sparc/regs/misc.hh @@ -174,8 +174,8 @@ struct STS const int NumMiscRegs = MISCREG_NUMMISCREGS; -inline constexpr RegClass miscRegClass(MiscRegClass, NumMiscRegs, - debug::MiscRegs); +inline constexpr RegClass miscRegClass(MiscRegClass, MiscRegClassName, + NumMiscRegs, debug::MiscRegs); } // namespace SparcISA } // namespace gem5 diff --git a/src/arch/x86/isa.cc b/src/arch/x86/isa.cc index b964a21c39..a3593b60eb 100644 --- a/src/arch/x86/isa.cc +++ b/src/arch/x86/isa.cc @@ -142,9 +142,10 @@ namespace { /* Not applicable to X86 */ -RegClass vecRegClass(VecRegClass, 1, debug::IntRegs); -RegClass vecElemClass(VecElemClass, 2, debug::IntRegs); -RegClass vecPredRegClass(VecPredRegClass, 1, debug::IntRegs); +RegClass vecRegClass(VecRegClass, VecRegClassName, 1, debug::IntRegs); +RegClass vecElemClass(VecElemClass, VecElemClassName, 2, debug::IntRegs); +RegClass vecPredRegClass(VecPredRegClass, VecPredRegClassName, 1, + debug::IntRegs); } // anonymous namespace diff --git a/src/arch/x86/regs/ccr.hh b/src/arch/x86/regs/ccr.hh index 383f026041..8433ade44a 100644 --- a/src/arch/x86/regs/ccr.hh +++ b/src/arch/x86/regs/ccr.hh @@ -61,8 +61,8 @@ enum : RegIndex } // namespace cc_reg -inline constexpr RegClass ccRegClass(CCRegClass, cc_reg::NumRegs, - debug::CCRegs); +inline constexpr RegClass ccRegClass(CCRegClass, CCRegClassName, + cc_reg::NumRegs, debug::CCRegs); namespace cc_reg { diff --git a/src/arch/x86/regs/float.hh b/src/arch/x86/regs/float.hh index e5150a9906..269626d2b3 100644 --- a/src/arch/x86/regs/float.hh +++ b/src/arch/x86/regs/float.hh @@ -121,8 +121,8 @@ enum FloatRegIndex } // namespace float_reg -inline constexpr RegClass floatRegClass(FloatRegClass, float_reg::NumRegs, - debug::FloatRegs); +inline constexpr RegClass floatRegClass(FloatRegClass, FloatRegClassName, + float_reg::NumRegs, debug::FloatRegs); namespace float_reg { diff --git a/src/arch/x86/regs/int.hh b/src/arch/x86/regs/int.hh index 9b7b8146db..989bb939d5 100644 --- a/src/arch/x86/regs/int.hh +++ b/src/arch/x86/regs/int.hh @@ -102,8 +102,8 @@ enum : RegIndex } // namespace int_reg -inline constexpr RegClass intRegClass(IntRegClass, int_reg::NumRegs, - debug::IntRegs); +inline constexpr RegClass intRegClass(IntRegClass, IntRegClassName, + int_reg::NumRegs, debug::IntRegs); namespace int_reg { diff --git a/src/arch/x86/regs/misc.hh b/src/arch/x86/regs/misc.hh index aa854e9787..3550384d06 100644 --- a/src/arch/x86/regs/misc.hh +++ b/src/arch/x86/regs/misc.hh @@ -538,8 +538,8 @@ segAttr(int index) } // namespace misc_reg -inline constexpr RegClass miscRegClass(MiscRegClass, misc_reg::NumRegs, - debug::MiscRegs); +inline constexpr RegClass miscRegClass(MiscRegClass, MiscRegClassName, + misc_reg::NumRegs, debug::MiscRegs); /** * A type to describe the condition code bits of the RFLAGS register, diff --git a/src/cpu/reg_class.cc b/src/cpu/reg_class.cc index 8764edf67b..12d1c7f2e0 100644 --- a/src/cpu/reg_class.cc +++ b/src/cpu/reg_class.cc @@ -71,14 +71,4 @@ RegClassOps::valString(const void *val, size_t size) const return printByteBuf(val, size, ByteOrder::big); } -const char *RegId::regClassStrings[] = { - "IntRegClass", - "FloatRegClass", - "VecRegClass", - "VecElemClass", - "VecPredRegClass", - "CCRegClass", - "MiscRegClass" -}; - } // namespace gem5 diff --git a/src/cpu/reg_class.hh b/src/cpu/reg_class.hh index 949531caf5..177b6fadc5 100644 --- a/src/cpu/reg_class.hh +++ b/src/cpu/reg_class.hh @@ -69,6 +69,15 @@ enum RegClassType InvalidRegClass = -1 }; +// "Standard" register class names. Using these is encouraged but optional. +inline constexpr char IntRegClassName[] = "integer"; +inline constexpr char FloatRegClassName[] = "floating_point"; +inline constexpr char VecRegClassName[] = "vector"; +inline constexpr char VecElemClassName[] = "vector_element"; +inline constexpr char VecPredRegClassName[] = "vector_predicate"; +inline constexpr char CCRegClassName[] = "condition_code"; +inline constexpr char MiscRegClassName[] = "miscellaneous"; + class RegId; class RegClassOps @@ -86,6 +95,7 @@ class RegClass { private: RegClassType _type; + const char *_name; size_t _numRegs; size_t _regBytes = sizeof(RegVal); @@ -99,9 +109,9 @@ class RegClass const debug::Flag &debugFlag; public: - constexpr RegClass(RegClassType type, size_t num_regs, - const debug::Flag &debug_flag) : - _type(type), _numRegs(num_regs), debugFlag(debug_flag) + constexpr RegClass(RegClassType type, const char *new_name, + size_t num_regs, const debug::Flag &debug_flag) : + _type(type), _name(new_name), _numRegs(num_regs), debugFlag(debug_flag) {} constexpr RegClass @@ -123,6 +133,7 @@ class RegClass } constexpr RegClassType type() const { return _type; } + constexpr const char *name() const { return _name; } constexpr size_t numRegs() const { return _numRegs; } constexpr size_t regBytes() const { return _regBytes; } constexpr size_t regShift() const { return _regShift; } @@ -144,7 +155,7 @@ class RegClass }; inline constexpr RegClass - invalidRegClass(InvalidRegClass, 0, debug::InvalidReg); + invalidRegClass(InvalidRegClass, "invalid", 0, debug::InvalidReg); /** Register ID: describe an architectural register with its class and index. * This structure is used instead of just the register index to disambiguate @@ -154,7 +165,6 @@ inline constexpr RegClass class RegId { protected: - static const char* regClassStrings[]; const RegClass *_regClass = nullptr; RegIndex regIdx; int numPinnedWrites; @@ -223,7 +233,7 @@ class RegId constexpr const char* className() const { - return regClassStrings[classValue()]; + return _regClass->name(); } int getNumPinnedWrites() const { return numPinnedWrites; }