arch: Implement StaticInst::advancePC(ThreadContext *) for the ISAs.

Change-Id: Icc0332eca55c38f80964e7f898ccfa35da64fdf9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52070
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/insts/macromem.hh

@@ -44,6 +44,7 @@
 #include "arch/arm/insts/pred_inst.hh"
 #include "arch/arm/pcstate.hh"
 #include "arch/arm/tlb.hh"
+#include "cpu/thread_context.hh"
 
 namespace gem5
 {
@@ -87,6 +88,20 @@ class MicroOp : public PredOp
             apc.advance();
         }
     }
+
+    void
+    advancePC(ThreadContext *tc) const override
+    {
+        PCState pc = tc->pcState().as<PCState>();
+        if (flags[IsLastMicroop]) {
+            pc.uEnd();
+        } else if (flags[IsMicroop]) {
+            pc.uAdvance();
+        } else {
+            pc.advance();
+        }
+        tc->pcState(pc);
+    }
 };
 
 class MicroOpX : public ArmStaticInst
@@ -109,6 +124,20 @@ class MicroOpX : public ArmStaticInst
             apc.advance();
         }
     }
+
+    void
+    advancePC(ThreadContext *tc) const override
+    {
+        PCState pc = tc->pcState().as<PCState>();
+        if (flags[IsLastMicroop]) {
+            pc.uEnd();
+        } else if (flags[IsMicroop]) {
+            pc.uAdvance();
+        } else {
+            pc.advance();
+        }
+        tc->pcState(pc);
+    }
 };
 
 /**

src/arch/arm/insts/mem.hh

@@ -43,6 +43,7 @@
 
 #include "arch/arm/insts/pred_inst.hh"
 #include "arch/arm/pcstate.hh"
+#include "cpu/thread_context.hh"
 
 namespace gem5
 {
@@ -69,6 +70,20 @@ class MightBeMicro : public PredOp
             apc.advance();
         }
     }
+
+    void
+    advancePC(ThreadContext *tc) const override
+    {
+        PCState pc = tc->pcState().as<PCState>();
+        if (flags[IsLastMicroop]) {
+            pc.uEnd();
+        } else if (flags[IsMicroop]) {
+            pc.uAdvance();
+        } else {
+            pc.advance();
+        }
+        tc->pcState(pc);
+    }
 };
 
 // The address is a base register plus an immediate.

src/arch/arm/insts/mem64.hh

@@ -41,6 +41,7 @@
 #include "arch/arm/insts/misc64.hh"
 #include "arch/arm/insts/static_inst.hh"
 #include "arch/arm/pcstate.hh"
+#include "cpu/thread_context.hh"
 
 namespace gem5
 {
@@ -87,6 +88,20 @@ class MightBeMicro64 : public ArmStaticInst
             apc.advance();
         }
     }
+
+    void
+    advancePC(ThreadContext *tc) const override
+    {
+        PCState pc = tc->pcState().as<PCState>();
+        if (flags[IsLastMicroop]) {
+            pc.uEnd();
+        } else if (flags[IsMicroop]) {
+            pc.uAdvance();
+        } else {
+            pc.advance();
+        }
+        tc->pcState(pc);
+    }
 };
 
 class Memory64 : public MightBeMicro64

src/arch/arm/insts/pred_inst.hh

@@ -46,6 +46,7 @@
 #include "base/compiler.hh"
 #include "base/logging.hh"
 #include "base/trace.hh"
+#include "cpu/thread_context.hh"
 
 namespace gem5
 {
@@ -400,6 +401,17 @@ class PredMicroop : public PredOp
         else
             apc.uAdvance();
     }
+
+    void
+    advancePC(ThreadContext *tc) const override
+    {
+        PCState pc = tc->pcState().as<PCState>();
+        if (flags[IsLastMicroop])
+            pc.uEnd();
+        else
+            pc.uAdvance();
+        tc->pcState(pc);
+    }
 };
 
 } // namespace ArmISA

src/arch/arm/insts/static_inst.hh

@@ -52,6 +52,7 @@
 #include "base/trace.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/static_inst.hh"
+#include "cpu/thread_context.hh"
 #include "sim/byteswap.hh"
 #include "sim/full_system.hh"
 
@@ -203,6 +204,14 @@ class ArmStaticInst : public StaticInst
         pcState.as<PCState>().advance();
     }
 
+    void
+    advancePC(ThreadContext *tc) const override
+    {
+        PCState pc = tc->pcState().as<PCState>();
+        pc.advance();
+        tc->pcState(pc);
+    }
+
     uint64_t getEMI() const override { return machInst; }
 
     std::unique_ptr<PCStateBase>

src/arch/arm/insts/vfp.hh

@@ -45,6 +45,7 @@
 #include "arch/arm/insts/misc.hh"
 #include "arch/arm/pcstate.hh"
 #include "arch/arm/regs/misc.hh"
+#include "cpu/thread_context.hh"
 
 namespace gem5
 {
@@ -866,6 +867,20 @@ class FpOp : public PredOp
         }
     }
 
+    void
+    advancePC(ThreadContext *tc) const override
+    {
+        PCState pc = tc->pcState().as<PCState>();
+        if (flags[IsLastMicroop]) {
+            pc.uEnd();
+        } else if (flags[IsMicroop]) {
+            pc.uAdvance();
+        } else {
+            pc.advance();
+        }
+        tc->pcState(pc);
+    }
+
     float
     fpSqrt (FPSCR fpscr,float x) const
     {

src/arch/mips/isa/base.isa

@@ -64,6 +64,14 @@ output header {{
             pc.as<PCState>().advance();
         }
 
+        void
+        advancePC(ThreadContext *tc) const override
+        {
+            PCState pc = tc->pcState().as<PCState>();
+            pc.advance();
+            tc->pcState(pc);
+        }
+
         std::unique_ptr<PCStateBase>
         buildRetPC(const PCStateBase &cur_pc,
                 const PCStateBase &call_pc) const override

src/arch/power/insts/static_inst.hh

@@ -33,6 +33,7 @@
 #include "arch/power/types.hh"
 #include "base/trace.hh"
 #include "cpu/static_inst.hh"
+#include "cpu/thread_context.hh"
 
 namespace gem5
 {
@@ -74,6 +75,14 @@ class PowerStaticInst : public StaticInst
         pc_state.as<PCState>().advance();
     }
 
+    void
+    advancePC(ThreadContext *tc) const override
+    {
+        PCState pc = tc->pcState().as<PCState>();
+        pc.advance();
+        tc->pcState(pc);
+    }
+
     std::unique_ptr<PCStateBase>
     buildRetPC(const PCStateBase &cur_pc,
             const PCStateBase &call_pc) const override

src/arch/riscv/insts/static_inst.cc

@@ -50,5 +50,17 @@ RiscvMicroInst::advancePC(PCStateBase &pcState) const
     }
 }
 
+void
+RiscvMicroInst::advancePC(ThreadContext *tc) const
+{
+    PCState pc = tc->pcState().as<PCState>();
+    if (flags[IsLastMicroop]) {
+        pc.uEnd();
+    } else {
+        pc.uAdvance();
+    }
+    tc->pcState(pc);
+}
+
 } // namespace RiscvISA
 } // namespace gem5

src/arch/riscv/insts/static_inst.hh

@@ -36,6 +36,7 @@
 #include "arch/riscv/types.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/static_inst.hh"
+#include "cpu/thread_context.hh"
 #include "mem/packet.hh"
 
 namespace gem5
@@ -64,6 +65,14 @@ class RiscvStaticInst : public StaticInst
         pc.as<PCState>().advance();
     }
 
+    void
+    advancePC(ThreadContext *tc) const override
+    {
+        PCState pc = tc->pcState().as<PCState>();
+        pc.advance();
+        tc->pcState(pc);
+    }
+
     std::unique_ptr<PCStateBase>
     buildRetPC(const PCStateBase &cur_pc,
             const PCStateBase &call_pc) const override
@@ -139,6 +148,7 @@ class RiscvMicroInst : public RiscvStaticInst
     }
 
     void advancePC(PCStateBase &pcState) const override;
+    void advancePC(ThreadContext *tc) const override;
 };
 
 } // namespace RiscvISA

src/arch/sparc/insts/micro.hh

@@ -109,6 +109,17 @@ class SparcMicroInst : public SparcStaticInst
         else
             spc.uAdvance();
     }
+
+    void
+    advancePC(ThreadContext *tc) const override
+    {
+        PCState pc = tc->pcState().as<PCState>();
+        if (flags[IsLastMicroop])
+            pc.uEnd();
+        else
+            pc.uAdvance();
+        tc->pcState(pc);
+    }
 };
 
 class SparcDelayedMicroInst : public SparcMicroInst

src/arch/sparc/insts/static_inst.cc

@@ -85,6 +85,14 @@ SparcStaticInst::advancePC(PCStateBase &pcState) const
     pcState.as<PCState>().advance();
 }
 
+void
+SparcStaticInst::advancePC(ThreadContext *tc) const
+{
+    PCState pc = tc->pcState().as<PCState>();
+    pc.advance();
+    tc->pcState(pc);
+}
+
 void
 SparcStaticInst::printSrcReg(std::ostream &os, int reg) const
 {

src/arch/sparc/insts/static_inst.hh

@@ -37,6 +37,7 @@
 #include "base/trace.hh"
 #include "cpu/exec_context.hh"
 #include "cpu/static_inst.hh"
+#include "cpu/thread_context.hh"
 
 namespace gem5
 {
@@ -112,6 +113,7 @@ class SparcStaticInst : public StaticInst
         const RegId *indexArray, int num) const;
 
     void advancePC(PCStateBase &pcState) const override;
+    void advancePC(ThreadContext *tc) const override;
 
     static bool passesFpCondition(uint32_t fcc, uint32_t condition);
     static bool passesCondition(uint32_t codes, uint32_t condition);

src/arch/x86/insts/microop.hh

@@ -142,6 +142,17 @@ class X86MicroopBase : public X86StaticInst
             xpc.uAdvance();
     }
 
+    void
+    advancePC(ThreadContext *tc) const override
+    {
+        PCState pc = tc->pcState().as<PCState>();
+        if (flags[IsLastMicroop])
+            pc.uEnd();
+        else
+            pc.uAdvance();
+        tc->pcState(pc);
+    }
+
     std::unique_ptr<PCStateBase> branchTarget(
             const PCStateBase &branch_pc) const override;
 

src/arch/x86/insts/static_inst.hh

@@ -42,6 +42,7 @@
 #include "arch/x86/types.hh"
 #include "base/trace.hh"
 #include "cpu/static_inst.hh"
+#include "cpu/thread_context.hh"
 #include "debug/X86.hh"
 
 namespace gem5
@@ -204,6 +205,14 @@ class X86StaticInst : public StaticInst
         pcState.as<PCState>().advance();
     }
 
+    void
+    advancePC(ThreadContext *tc) const override
+    {
+        PCState pc = tc->pcState().as<PCState>();
+        pc.advance();
+        tc->pcState(pc);
+    }
+
     std::unique_ptr<PCStateBase>
     buildRetPC(const PCStateBase &cur_pc,
             const PCStateBase &call_pc) const override