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arch,cpu: Convert ExecContext::pcState to use PCStateBase.

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Some places need persistent temporaries for the return values of
ThreadContext::pcState(), which is currently by value.

Change-Id: Icd4924f1d16ebe1c99c54ed47616733422340cfe
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/52057
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-10-14 03:49:06 -07:00
parent a9b75bed05
commit 39584edc72
12 changed files with 45 additions and 33 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/arch/arm/insts/pseudo.cc
View File

@@ -60,8 +60,7 @@ DecoderFaultInst::DecoderFaultInst(ExtMachInst _machInst)
Fault
DecoderFaultInst::execute(ExecContext *xc, Trace::InstRecord *traceData) const
{
const PCState pc_state(xc->pcState());
const Addr pc(pc_state.instAddr());
const Addr pc = xc->pcState().instAddr();
switch (faultId) {
case DecoderFault::UNALIGNED:
@@ -203,7 +202,7 @@ DebugStep::DebugStep(ExtMachInst _machInst)
Fault
DebugStep::execute(ExecContext *xc, Trace::InstRecord *traceData) const
{
PCState pc_state(xc->pcState());
PCState pc_state = xc->pcState().as<PCState>();
pc_state.debugStep(false);
xc->pcState(pc_state);
@@ -213,7 +212,6 @@ DebugStep::execute(ExecContext *xc, Trace::InstRecord *traceData) const
return std::make_shared<SoftwareStepFault>(machInst, ldx,
pc_state.stepped());
}
} // namespace gem5

8
src/arch/arm/insts/static_inst.hh
View File

@@ -325,13 +325,13 @@ class ArmStaticInst : public StaticInst
static inline Addr
readPC(ExecContext *xc)
{
return xc->pcState().instPC();
return xc->pcState().as<PCState>().instPC();
}
static inline void
setNextPC(ExecContext *xc, Addr val)
{
PCState pc = xc->pcState();
PCState pc = xc->pcState().as<PCState>();
pc.instNPC(val);
xc->pcState(pc);
}
@@ -374,7 +374,7 @@ class ArmStaticInst : public StaticInst
static inline void
setIWNextPC(ExecContext *xc, Addr val)
{
PCState pc = xc->pcState();
PCState pc = xc->pcState().as<PCState>();
pc.instIWNPC(val);
xc->pcState(pc);
}
@@ -384,7 +384,7 @@ class ArmStaticInst : public StaticInst
static inline void
setAIWNextPC(ExecContext *xc, Addr val)
{
PCState pc = xc->pcState();
PCState pc = xc->pcState().as<PCState>();
pc.instAIWNPC(val);
xc->pcState(pc);
}

3
src/arch/isa_parser/isa_parser.py
View File

@@ -152,7 +152,8 @@ class Template(object):
myDict['op_rd'] = operands.concatAttrStrings('op_rd')
if operands.readPC:
myDict['op_rd'] = '__parserAutoPCState = xc->pcState();\n' + \
myDict['op_rd'] = \
'set(__parserAutoPCState, xc->pcState());\n' + \
myDict['op_rd']
# Compose the op_wb string. If we're going to write back the

5
src/arch/isa_parser/operand_types.py
View File

@@ -751,7 +751,8 @@ class PCStateOperand(Operand):
(self.base_name, self.reg_spec)
else:
# The whole PC state itself.
return '%s = xc->pcState();\n' % self.base_name
return f'{self.base_name} = ' \
f'xc->pcState().as<{self.parser.namespace}::PCState>();\n'
def makeWrite(self, predWrite):
if self.reg_spec:
@@ -760,7 +761,7 @@ class PCStateOperand(Operand):
(self.reg_spec, self.base_name)
else:
# The whole PC state itself.
return 'xc->pcState(%s);\n' % self.base_name
return f'xc->pcState({self.base_name});\n'
def makeDecl(self):
ctype = f'{self.parser.namespace}::PCState'

4
src/arch/power/isa/formats/unknown.isa
View File

@@ -72,9 +72,9 @@ output exec {{
Fault
Unknown::execute(ExecContext *xc, Trace::InstRecord *traceData) const
{
inform("attempt to execute unknown instruction at %#x"
inform("attempt to execute unknown instruction at %s"
"(inst 0x%08x, opcode 0x%x, binary: %s)",
xc->pcState().pc(), machInst, PO, inst2string(machInst));
xc->pcState(), machInst, PO, inst2string(machInst));
return std::make_shared<UnimplementedOpcodeFault>();
}
}};

5
src/arch/riscv/faults.hh
View File

@@ -243,8 +243,9 @@ class BreakpointFault : public RiscvFault
const PCState pcState;
public:
BreakpointFault(const PCState &pc)
: RiscvFault("Breakpoint", FaultType::OTHERS, BREAKPOINT), pcState(pc)
BreakpointFault(const PCStateBase &pc)
: RiscvFault("Breakpoint", FaultType::OTHERS, BREAKPOINT),
pcState(pc.as<PCState>())
{}
RegVal trap_value() const override { return pcState.pc(); }

12
src/cpu/checker/cpu.hh
View File

@@ -354,13 +354,19 @@ class CheckerCPU : public BaseCPU, public ExecContext
return (thread->htmTransactionStarts - thread->htmTransactionStops);
}
TheISA::PCState pcState() const override { return thread->pcState(); }
mutable TheISA::PCState tempPCState;
const PCStateBase &
pcState() const override
{
set(tempPCState, thread->pcState());
return tempPCState;
}
void
pcState(const TheISA::PCState &val) override
pcState(const PCStateBase &val) override
{
DPRINTF(Checker, "Changing PC to %s, old PC %s.\n",
val, thread->pcState());
thread->pcState(val);
thread->pcState(val.as<TheISA::PCState>());
}
Addr instAddr() { return thread->instAddr(); }
MicroPC microPC() { return thread->microPC(); }

4
src/cpu/exec_context.hh
View File

@@ -181,8 +181,8 @@ class ExecContext
* @{
* @name PC Control
*/
virtual TheISA::PCState pcState() const = 0;
virtual void pcState(const TheISA::PCState &val) = 0;
virtual const PCStateBase &pcState() const = 0;
virtual void pcState(const PCStateBase &val) = 0;
/** @} */
/**

12
src/cpu/minor/exec_context.hh
View File

@@ -94,7 +94,7 @@ class ExecContext : public gem5::ExecContext
inst(inst_)
{
DPRINTF(MinorExecute, "ExecContext setting PC: %s\n", *inst->pc);
pcState(inst->pc->as<TheISA::PCState>());
pcState(*inst->pc);
setPredicate(inst->readPredicate());
setMemAccPredicate(inst->readMemAccPredicate());
thread.setIntReg(zeroReg, 0);
@@ -299,16 +299,18 @@ class ExecContext : public gem5::ExecContext
return 0;
}
TheISA::PCState
mutable TheISA::PCState tempPCState;
const PCStateBase &
pcState() const override
{
return thread.pcState();
set(tempPCState, thread.pcState());
return tempPCState;
}
void
pcState(const TheISA::PCState &val) override
pcState(const PCStateBase &val) override
{
thread.pcState(val);
thread.pcState(val.as<TheISA::PCState>());
}
RegVal

6
src/cpu/o3/dyn_inst.hh
View File

@@ -898,14 +898,14 @@ class DynInst : public ExecContext, public RefCounted
}
/** Read the PC state of this instruction. */
TheISA::PCState
const PCStateBase &
pcState() const override
{
return pc->as<TheISA::PCState>();
return *pc;
}
/** Set the PC state of this instruction. */
void pcState(const TheISA::PCState &val) override { set(pc, val); }
void pcState(const PCStateBase &val) override { set(pc, val); }
/** Read the PC of this instruction. */
Addr instAddr() const { return pc->instAddr(); }

3
src/cpu/o3/iew.cc
View File

@@ -461,7 +461,8 @@ IEW::squashDueToBranch(const DynInstPtr& inst, ThreadID tid)
inst->seqNum < toCommit->squashedSeqNum[tid]) {
toCommit->squash[tid] = true;
toCommit->squashedSeqNum[tid] = inst->seqNum;
toCommit->branchTaken[tid] = inst->pcState().branching();
toCommit->branchTaken[tid] =
inst->pcState().as<TheISA::PCState>().branching();
set(toCommit->pc[tid], inst->pcState());
inst->staticInst->advancePC(*toCommit->pc[tid]);

10
src/cpu/simple/exec_context.hh
View File

@@ -467,16 +467,18 @@ class SimpleExecContext : public ExecContext
thread->setMiscReg(misc_reg, val);
}
TheISA::PCState
mutable TheISA::PCState tempPCState;
const PCStateBase &
pcState() const override
{
return thread->pcState();
set(tempPCState, thread->pcState());
return tempPCState;
}
void
pcState(const TheISA::PCState &val) override
pcState(const PCStateBase &val) override
{
thread->pcState(val);
thread->pcState(val.as<TheISA::PCState>());
}
Fault