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  • 2a525325df arch: Delete now unused operand types. Gabe Black 2021-08-21 06:38:03 -07:00
  • ae8e8e2d3c arch: Pass through the actual base class in OperandDesc. Gabe Black 2022-03-08 21:29:13 -08:00
  • 1856bec959 arch: Remove support for lists in def operands. Gabe Black 2021-08-21 06:33:03 -07:00
  • 7103088310 arch-sparc: Use the OperandDesc classes in the ISA description. Gabe Black 2021-08-21 06:13:06 -07:00
  • abdf573c53 arch-power: Use the OperandDesc classes in the ISA description. Gabe Black 2021-08-21 06:06:22 -07:00
  • d6905bb6d0 arch-mips: Use the OperandDesc classes in the ISA description. Gabe Black 2021-08-21 06:06:02 -07:00
  • 7f525d4690 arch-arm: Use the new OperandDesc classes in the ISA description. Gabe Black 2021-08-21 06:03:05 -07:00
  • a118361e46 arch-riscv: Use the OperandDesc classes in the ISA description. Gabe Black 2021-08-21 06:09:18 -07:00
  • 988f7573f6 arch: Create a new operand desc type which takes a class as a parameter. Gabe Black 2021-08-21 04:58:25 -07:00
  • 9993440a8e arch-x86: Use the new operand desc classes in the ISA description. Gabe Black 2021-08-21 04:50:30 -07:00
  • 23e6607507 mem: Fix phy mem with shm and multiple abstr mem Jui-min Lee 2022-03-07 17:49:39 +08:00
  • 288e5c47fa mem: Create a SysBridge object to bridge between Systems interconnect. Gabe Black 2021-12-04 04:02:00 -08:00
  • 14b60f4c39 stdlib: Cache the resources.json download Bobby R. Bruce 2022-03-02 11:31:26 -08:00
  • 02f22d65a7 stdlib: Update the downloader to retry on failure Bobby R. Bruce 2022-03-02 11:15:35 -08:00
  • fc59c6e4e8 arch-arm: Create a magic PendingDvm operand Giacomo Travaglini 2021-11-01 15:25:40 +00:00
  • 5b76001b54 arch-arm: Add helper MISCREG to track a pending DVM operation Samuel Stark 2021-10-25 16:43:00 +01:00
  • 139f635bde cpu: Allow TLB shootdown requests in the o3 cpu Samuel Stark 2021-09-22 13:46:32 +01:00
  • 9dfac01243 cpu: Allow TLB shootdown requests in the timing cpu Samuel Stark 2021-10-26 14:57:05 +01:00
  • de9cdc28ce cpu: Rename initiateHtmCmd to be more generic Samuel Stark 2021-09-21 17:32:01 +01:00
  • a84c987eef arch: Add desc subclasses for the various operand types. Gabe Black 2021-08-21 04:48:05 -07:00
  • 4a3a1b92b4 arch: Put operand properties into an object constructed with the list. Gabe Black 2021-08-21 03:51:49 -07:00
  • 38e06033fa arch: Consolidate most of the RegVal based operands into a base class. Gabe Black 2021-08-21 02:45:47 -07:00
  • 650cee911c dev: Fix -Werror=unused-variable in QEMU config device Giacomo Travaglini 2022-03-07 09:47:02 +00:00
  • 38abefd9d3 systemc: Fix memory leak of sc_event_list Jui-min Lee 2022-03-07 11:16:46 +08:00
  • 2fcb7ae87e configs: Add O3 option in starter_fs.py and ruby_fs.py Giacomo Travaglini 2019-02-14 11:53:06 +00:00
  • f161c0b6bc dev: Add a base QEMU firmware config device. Gabe Black 2022-01-18 21:12:03 -08:00
  • cbc55aeff0 arch-x86: Fix the immediate size for the 0x9a one byte opcode. Gabe Black 2022-01-18 21:07:42 -08:00
  • e04d40828c arch-x86: Don't decode SIB bytes in 32 bit mode. Gabe Black 2022-01-16 11:46:50 -08:00
  • 94bb3291fa arch-x86: Truncate RIPs properly in the wrip microop. Gabe Black 2022-01-16 11:24:12 -08:00
  • 911a8762e8 arch-x86: Correct how default segments are handled. Gabe Black 2022-01-16 11:20:17 -08:00
  • cbb495334c cpu: Make getIsaPtr const. Gabe Black 2021-09-11 00:03:52 -07:00
  • 9e8d397411 configs: Remove unused caches in ruby_fs.py Giacomo Travaglini 2022-03-02 17:05:44 +00:00
  • 01785b5d0e mem-ruby: Reset stats in Ruby correctly Jason Lowe-Power 2022-03-01 15:47:39 -08:00
  • c0d380b4d7 arch: Simplify the VecElemOperand class. Gabe Black 2021-08-21 00:23:29 -07:00
  • 81d2f9f10a arch: Consolidate all the make_constructor methods in the ISA parser. Gabe Black 2021-08-20 22:11:11 -07:00
  • 6de0156cf7 mem-cache: Avoid calling .front() on a possibly empty std::list Alex Richardson 2022-03-01 13:38:12 +00:00
  • a3e481c024 cpu: Fix SimpleExecContext coding style Giacomo Travaglini 2021-10-26 15:47:25 +01:00
  • 77263615db mem: Add TLB invalidation flags to the Request object Samuel Stark 2021-10-25 16:43:00 +01:00
  • a00f6d67d4 arch-arm: Implement TLBI instructions with a separate class Giacomo Travaglini 2021-10-25 15:01:11 +01:00
  • f36c5d778b arch-arm: Implement DSB Shareable with a separate class Giacomo Travaglini 2021-10-22 15:07:34 +01:00
  • 154884dea3 sim: Avoid -Werror=unused-variable in bufval unittests Giacomo Travaglini 2022-03-01 10:27:22 +00:00
  • f1b421baf5 arch: Get rid of the is${Type}Reg methods of the Operand class. Gabe Black 2021-08-20 21:47:17 -07:00
  • d8e04d25a6 arch: Introduce an intermediate RegOperand class in operand_types.py. Gabe Black 2021-08-20 21:43:57 -07:00
  • efdba6d353 cpu-o3: Initialize register maps and free lists with loops. Gabe Black 2021-08-20 21:36:38 -07:00
  • 56fba14e7d cpu-o3: Manage per-register-type free lists with an array. Gabe Black 2021-08-20 20:43:58 -07:00
  • 5e721db9a2 arch-vega: Handle signed offsets in Global/Scratch instructions Kyle Roarty 2022-02-28 18:40:54 -06:00
  • 0d65662218 arch-arm: Reuse MCR15 trapping code in DC instructions Giacomo Travaglini 2021-12-21 12:15:02 +00:00
  • 31c31e1cd8 arch-arm: Replace mcrMrc15TrapToHyp with mcrMrc15Trap Giacomo Travaglini 2021-12-21 10:58:01 +00:00
  • 412ae3f8df cpu,sim: Don't tie ThreadContext contextId to the CPU ID. Gabe Black 2022-02-24 02:15:52 -08:00
  • e7f1acc0dc scons: Add a "mold" value to the --linker option. Gabe Black 2022-02-25 23:12:17 -08:00
  • 76c0466557 cpu-o3: Use an array to hold rename maps in UnifiedRenameMap. Gabe Black 2021-08-20 20:23:42 -07:00
  • 39d25eebd0 cpu-o3: Make canRename extract register counts locally. Gabe Black 2021-08-20 19:56:24 -07:00
  • a5ab19d3ef arch,cpu: Replace num${Type}DestReg accessors with numDestReg(type). Gabe Black 2021-08-20 19:43:38 -07:00
  • 967bada8db arch,cpu: Replace StaticInst::_num${TYPE}DestRegs members with an array. Gabe Black 2021-08-20 19:30:16 -07:00
  • 2d012222c2 arch: Get rid of the unused numAccessNeeded variable. Gabe Black 2021-08-20 21:38:28 -07:00
  • ec4d6c0daf cpu,arch-arm: Use a sentry class valid for invalid RegIds. Gabe Black 2021-08-14 02:50:25 -07:00
  • 092d33f3f5 configs: Modify createAddrRanges to support NUMA configuration Daecheol You 2022-02-09 18:41:22 +09:00
  • 0fefc76fe6 mem-cache: Fix unit inconsistencies in base cache stats Hoa Nguyen 2022-02-18 17:05:37 -08:00
  • f32130e26f arch-x86: Implement interrupts in real mode. Gabe Black 2022-01-20 22:15:35 -08:00
  • 6a9dfcef52 mem-ruby: Revert 7018c2b34 Matthew Poremba 2022-02-24 11:34:49 -08:00
  • 97bc68e6f4 arch-x86: Fix how flags registers are handled in IRET_REAL. Gabe Black 2022-01-20 22:14:02 -08:00
  • 7dfca8531d cpu: Remove an unused variable from one of the branch predictors. Gabe Black 2022-02-25 23:11:18 -08:00
  • 293cfab778 arch-x86: Mark a variable as [[maybe_unused]]. Gabe Black 2022-02-25 23:09:39 -08:00
  • 001e17890c misc: Use the new bufval helpers in RegClass and Packet. Gabe Black 2022-02-25 05:01:09 -08:00
  • 9df4159456 sim: Add some helpers for working with values in buffers. Gabe Black 2022-02-25 04:59:58 -08:00
  • 7f9f145174 arch-x86: Implement the real mode far return that takes an immediate. Gabe Black 2022-01-17 00:59:22 -08:00
  • 2a424850d5 arch-x86: Don't load past the end of the far pointer in real mode jmp. Gabe Black 2022-01-17 00:27:52 -08:00
  • d73ce0f593 arch-x86: Implement real mode far call. Gabe Black 2022-01-17 00:27:23 -08:00
  • 7468d4169c arch-x86: Straighten out the segment and selector for real far jumps. Gabe Black 2022-01-16 11:23:31 -08:00
  • 802f14bb52 arch-x86: Implement popping into a stack selector in real mode. Gabe Black 2022-01-16 11:22:38 -08:00
  • c2c10dc647 arch-x86: Implement the real mode versions of LDS, LES, etc. Gabe Black 2022-01-16 02:18:50 -08:00
  • aa4b6047e5 cpu-simple: Ignore writes to the "zero" register. Gabe Black 2021-08-14 01:28:45 -07:00
  • f12c330f40 arch-x86: Use different tables for 64 bit prefixes in the decoder. Gabe Black 2022-01-16 01:33:33 -08:00
  • 7a408e35fd dev,arch-x86: Add an x86/compatibility IDE controller. Gabe Black 2022-01-16 01:15:04 -08:00
  • 2bbcee7723 dev: Fix an assert in the I8259 interrupt controller. Gabe Black 2022-01-16 01:09:10 -08:00
  • 72a455f9c9 dev: Don't implement the ATAPI_IDENTIFY_DEVICE command. Gabe Black 2022-01-14 02:59:39 -08:00
  • 5df52e0dca arch-x86: Overhaul how address size is handled, particularly for stack. Gabe Black 2022-01-10 21:02:27 -08:00
  • 375236082d scons: Use env and not main in SConscripts. Gabe Black 2022-02-16 03:12:03 -08:00
  • e5281da388 sim: Fix style in insttracer.hh. Gabe Black 2021-08-11 05:21:32 -07:00
  • 3e846d20ed cpu: Remove VecRegContainer from ThreadContext::compare. Gabe Black 2021-08-12 01:54:14 -07:00
  • b5edb3b0e4 cpu-o3: Print vec and vec pred reg values with valString. Gabe Black 2021-08-11 05:14:13 -07:00
  • 9950d58e16 cpu-o3: Remove some unused accessors on the PhysRegFile. Gabe Black 2021-08-11 05:07:58 -07:00
  • 0eff31e564 arch-riscv: Fix a typo in fsgnjn_s decoder ksco 2022-02-23 21:49:12 +08:00
  • 3ba623d673 arch: Stop using TheISA:: in the ISA parser. Gabe Black 2021-08-11 05:52:25 -07:00
  • d53f75c1eb cpu: Eliminate the (read|set)VecPredReg helpers from ThreadContext. Gabe Black 2021-08-11 03:59:27 -07:00
  • 5c3a6a4e13 cpu,arm: Eliminate the now unused helpers (read|set)VecPredReg. Gabe Black 2021-08-11 03:30:26 -07:00
  • eefe075d3b arm: Replace readVecPredReg with getReg in the tarmac tracer. Gabe Black 2021-08-11 03:50:28 -07:00
  • 22eeeaff86 cpu: Remove readVecPredReg from ThreadContext::compare. Gabe Black 2021-08-11 03:40:48 -07:00
  • 973d9c82c0 arm: Collapse (set|read)VecPredReg in htm.cc. Gabe Black 2021-08-11 03:29:03 -07:00
  • 40b9c0d2bd cpu: Remove the default implementation of (get|set)RegFlat. Gabe Black 2021-08-11 01:40:11 -07:00
  • ae10990287 cpu: Use arrays and abstraction to handle regs in SimpleThread. Gabe Black 2021-08-10 23:15:13 -07:00
  • 64171d4d14 cpu,arch: Attach a debug flag to each RegClass. Gabe Black 2021-08-11 04:34:31 -07:00
  • 322f1d8fe7 arm: Use custom RegClassOps for vector and vector pred registers. Gabe Black 2021-08-11 03:25:02 -07:00
  • 6cc3a27e09 arch-x86: Fix some settings installed by the init interrupt. Gabe Black 2022-02-22 23:45:19 -08:00
  • 70ee16a387 arch-x86: Propogate the unusable bit to KVM. Gabe Black 2022-02-22 23:44:23 -08:00
  • 0e65df2cf5 arch-x86: Respect LDT and TR bases in long mode. Gabe Black 2022-02-22 23:43:14 -08:00
  • 85b769a68e cpu,arm: Add a method to RegClass-es to print register values. Gabe Black 2021-08-11 03:03:10 -07:00
  • ff4a8b15a0 scons: Handle TARGET_GPU_ISA not being set. Gabe Black 2022-02-16 22:14:37 -08:00
  • 52485bbc38 dev: Make VirtIORng device use gem5's rng instead of C++'s Hoa Nguyen 2022-02-16 15:59:08 -08:00
  • b4ba4916dd cpu: Handle Request::NO_ACCESS flag in MinorCPU and O3CPU Giacomo Travaglini 2021-10-28 11:44:36 +01:00