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cpu-o3: Initialize register maps and free lists with loops.

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Now that these can be referenced by index instead of by a fixed name, we
can manage them more generically using loops.

Change-Id: I7bb7a6b712ee66f22fa809feef4abfcd1851f237
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49717
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-08-20 21:36:38 -07:00
parent 56fba14e7d
commit efdba6d353
1 changed files with 18 additions and 66 deletions
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84
src/cpu/o3/cpu.cc
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@@ -225,53 +225,17 @@ CPU::CPU(const BaseO3CPUParams &params)
// Initialize rename map to assign physical registers to the
// architectural registers for active threads only.
for (ThreadID tid = 0; tid < active_threads; tid++) {
for (RegIndex ridx = 0; ridx < regClasses.at(IntRegClass).numRegs();
++ridx) {
// Note that we can't use the rename() method because we don't
// want special treatment for the zero register at this point
PhysRegIdPtr phys_reg = freeList.getReg(IntRegClass);
renameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg);
commitRenameMap[tid].setEntry(RegId(IntRegClass, ridx), phys_reg);
}
for (RegIndex ridx = 0; ridx < regClasses.at(FloatRegClass).numRegs();
++ridx) {
PhysRegIdPtr phys_reg = freeList.getReg(FloatRegClass);
renameMap[tid].setEntry(RegId(FloatRegClass, ridx), phys_reg);
commitRenameMap[tid].setEntry(
RegId(FloatRegClass, ridx), phys_reg);
}
const size_t numVecs = regClasses.at(VecRegClass).numRegs();
/* Initialize the full-vector interface */
for (RegIndex ridx = 0; ridx < numVecs; ++ridx) {
RegId rid = RegId(VecRegClass, ridx);
PhysRegIdPtr phys_reg = freeList.getReg(VecRegClass);
renameMap[tid].setEntry(rid, phys_reg);
commitRenameMap[tid].setEntry(rid, phys_reg);
}
/* Initialize the vector-element interface */
const size_t numElems = regClasses.at(VecElemClass).numRegs();
for (RegIndex ridx = 0; ridx < numElems; ++ridx) {
RegId lrid = RegId(VecElemClass, ridx);
PhysRegIdPtr phys_elem = freeList.getReg(VecElemClass);
renameMap[tid].setEntry(lrid, phys_elem);
commitRenameMap[tid].setEntry(lrid, phys_elem);
}
for (RegIndex ridx = 0;
ridx < regClasses.at(VecPredRegClass).numRegs(); ++ridx) {
PhysRegIdPtr phys_reg = freeList.getReg(VecPredRegClass);
renameMap[tid].setEntry(RegId(VecPredRegClass, ridx), phys_reg);
commitRenameMap[tid].setEntry(
RegId(VecPredRegClass, ridx), phys_reg);
}
for (RegIndex ridx = 0; ridx < regClasses.at(CCRegClass).numRegs();
++ridx) {
PhysRegIdPtr phys_reg = freeList.getReg(CCRegClass);
renameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg);
commitRenameMap[tid].setEntry(RegId(CCRegClass, ridx), phys_reg);
for (auto type = (RegClassType)0; type <= CCRegClass;
type = (RegClassType)(type + 1)) {
for (RegIndex ridx = 0; ridx < regClasses.at(type).numRegs();
++ridx) {
// Note that we can't use the rename() method because we don't
// want special treatment for the zero register at this point
RegId rid = RegId(type, ridx);
PhysRegIdPtr phys_reg = freeList.getReg(type);
renameMap[tid].setEntry(rid, phys_reg);
commitRenameMap[tid].setEntry(rid, phys_reg);
}
}
}
@@ -729,25 +693,13 @@ CPU::insertThread(ThreadID tid)
//Bind Int Regs to Rename Map
const auto &regClasses = isa[tid]->regClasses();
for (RegIndex idx = 0; idx < regClasses.at(IntRegClass).numRegs(); idx++) {
PhysRegIdPtr phys_reg = freeList.getReg(IntRegClass);
renameMap[tid].setEntry(RegId(IntRegClass, idx), phys_reg);
scoreboard.setReg(phys_reg);
}
//Bind Float Regs to Rename Map
for (RegIndex idx = 0; idx < regClasses.at(FloatRegClass).numRegs();
idx++) {
PhysRegIdPtr phys_reg = freeList.getReg(FloatRegClass);
renameMap[tid].setEntry(RegId(FloatRegClass, idx), phys_reg);
scoreboard.setReg(phys_reg);
}
//Bind condition-code Regs to Rename Map
for (RegIndex idx = 0; idx < regClasses.at(CCRegClass).numRegs(); idx++) {
PhysRegIdPtr phys_reg = freeList.getReg(CCRegClass);
renameMap[tid].setEntry(RegId(CCRegClass, idx), phys_reg);
scoreboard.setReg(phys_reg);
for (auto type = (RegClassType)0; type <= CCRegClass;
type = (RegClassType)(type + 1)) {
for (RegIndex idx = 0; idx < regClasses.at(type).numRegs(); idx++) {
PhysRegIdPtr phys_reg = freeList.getReg(type);
renameMap[tid].setEntry(RegId(type, idx), phys_reg);
scoreboard.setReg(phys_reg);
}
}
//Copy Thread Data Into RegFile