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arm: Replace readVecPredReg with getReg in the tarmac tracer.

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Change-Id: Id290b4b63ca0cf9982327e1451d12917e9d99272
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49701
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-08-11 03:50:28 -07:00
parent 22eeeaff86
commit eefe075d3b
2 changed files with 4 additions and 4 deletions
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4
src/arch/arm/tracers/tarmac_parser.cc
View File

@@ -786,8 +786,8 @@ TarmacParserRecord::TarmacParserRecordEvent::process()
break;
case REG_P:
{
const ArmISA::VecPredRegContainer& pc =
thread->readVecPredReg(RegId(VecPredRegClass, it->index));
ArmISA::VecPredRegContainer pc;
thread->getReg(RegId(VecPredRegClass, it->index), &pc);
auto pv = pc.as<uint8_t>();
uint64_t p = 0;
for (int i = maxVectorLength * 8; i > 0; ) {

4
src/arch/arm/tracers/tarmac_record_v8.cc
View File

@@ -163,8 +163,8 @@ TarmacTracerRecordV8::TraceRegEntryV8::updatePred(
)
{
auto thread = tarmCtx.thread;
const auto& pred_container = thread->readVecPredReg(
RegId(regClass, regRelIdx));
ArmISA::VecPredRegContainer pred_container;
thread->getReg(RegId(regClass, regRelIdx), &pred_container);
// Predicate registers are always 1/8 the size of related vector
// registers. (getCurSveVecLenInBits(thread) / 8)