diff --git a/src/arch/arm/tracers/tarmac_parser.cc b/src/arch/arm/tracers/tarmac_parser.cc
index e8909a02ad..7abe1c204c 100644
--- a/src/arch/arm/tracers/tarmac_parser.cc
+++ b/src/arch/arm/tracers/tarmac_parser.cc
@@ -786,8 +786,8 @@ TarmacParserRecord::TarmacParserRecordEvent::process()
             break;
           case REG_P:
             {
-                const ArmISA::VecPredRegContainer& pc =
-                    thread->readVecPredReg(RegId(VecPredRegClass, it->index));
+                ArmISA::VecPredRegContainer pc;
+                thread->getReg(RegId(VecPredRegClass, it->index), &pc);
                 auto pv = pc.as<uint8_t>();
                 uint64_t p = 0;
                 for (int i = maxVectorLength * 8; i > 0; ) {
diff --git a/src/arch/arm/tracers/tarmac_record_v8.cc b/src/arch/arm/tracers/tarmac_record_v8.cc
index 8dd96d131b..f34a183115 100644
--- a/src/arch/arm/tracers/tarmac_record_v8.cc
+++ b/src/arch/arm/tracers/tarmac_record_v8.cc
@@ -163,8 +163,8 @@ TarmacTracerRecordV8::TraceRegEntryV8::updatePred(
 )
 {
     auto thread = tarmCtx.thread;
-    const auto& pred_container = thread->readVecPredReg(
-        RegId(regClass, regRelIdx));
+    ArmISA::VecPredRegContainer pred_container;
+    thread->getReg(RegId(regClass, regRelIdx), &pred_container);
 
     // Predicate registers are always 1/8 the size of related vector
     // registers. (getCurSveVecLenInBits(thread) / 8)