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arch-arm: Replace mcrMrc15TrapToHyp with mcrMrc15Trap

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The mcrMrc15TrapToHyp helper is already called within mcrMrc15Trap
This achieves the following:

1) Simplifies ISA code
2) Aligns McrDc to Mcr instruction

Change-Id: I9b6bc621ad89230ad9dcf0563d8985d5757b4ae1
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56592
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2021-12-21 10:58:01 +00:00
parent 412ae3f8df
commit 31c31e1cd8
2 changed files with 10 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files

19
src/arch/arm/insts/misc.cc
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2010, 2012-2013, 2017-2018 ARM Limited
* Copyright (c) 2010, 2012-2013, 2017-2018, 2021 Arm Limited
* Copyright (c) 2013 Advanced Micro Devices, Inc.
* All rights reserved
*
@@ -362,14 +362,7 @@ McrMrcMiscInst::McrMrcMiscInst(const char *_mnemonic, ExtMachInst _machInst,
Fault
McrMrcMiscInst::execute(ExecContext *xc, Trace::InstRecord *traceData) const
{
bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), iss);
if (hypTrap) {
return std::make_shared<HypervisorTrap>(machInst, iss,
EC_TRAPPED_CP15_MCR_MRC);
} else {
return NoFault;
}
return mcrMrc15Trap(miscReg, machInst, xc->tcBase(), iss);
}
std::string
@@ -388,11 +381,9 @@ McrMrcImplDefined::McrMrcImplDefined(const char *_mnemonic,
Fault
McrMrcImplDefined::execute(ExecContext *xc, Trace::InstRecord *traceData) const
{
bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), iss);
if (hypTrap) {
return std::make_shared<HypervisorTrap>(machInst, iss,
EC_TRAPPED_CP15_MCR_MRC);
Fault fault = mcrMrc15Trap(miscReg, machInst, xc->tcBase(), iss);
if (fault != NoFault) {
return fault;
} else {
return std::make_shared<UndefinedInstruction>(machInst, false,
mnemonic);

11
src/arch/arm/isa/insts/misc.isa
View File

@@ -1,6 +1,6 @@
// -*- mode:c++ -*-
// Copyright (c) 2010-2013,2017-2020 ARM Limited
// Copyright (c) 2010-2013,2017-2021 Arm Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
@@ -1115,7 +1115,7 @@ let {{
MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
RegId(MiscRegClass, preFlatDest)).index();
bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), imm);
Fault fault = mcrMrc15Trap(miscReg, machInst, xc->tcBase(), imm);
auto [can_write, undefined] = canWriteCoprocReg(miscReg, Scr, Cpsr,
xc->tcBase());
@@ -1123,14 +1123,13 @@ let {{
// if we're in non secure PL1 mode then we can trap regardless
// of whether the register is accessible, in other modes we
// trap if only if the register IS accessible.
if (undefined || (!can_write & !(hypTrap & !inUserMode(Cpsr) &
if (undefined || (!can_write && !(fault != NoFault && !inUserMode(Cpsr) &&
!isSecure(xc->tcBase())))) {
return std::make_shared<UndefinedInstruction>(machInst, false,
mnemonic);
}
if (hypTrap) {
return std::make_shared<HypervisorTrap>(machInst, imm,
EC_TRAPPED_CP15_MCR_MRC);
if (fault != NoFault) {
return fault;
}
'''