diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index 4bb02c98e0..8c46cb8965 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -1,5 +1,5 @@
 /*
- * Copyright (c) 2010, 2012-2013, 2017-2018 ARM Limited
+ * Copyright (c) 2010, 2012-2013, 2017-2018, 2021 Arm Limited
  * Copyright (c) 2013 Advanced Micro Devices, Inc.
  * All rights reserved
  *
@@ -362,14 +362,7 @@ McrMrcMiscInst::McrMrcMiscInst(const char *_mnemonic, ExtMachInst _machInst,
 Fault
 McrMrcMiscInst::execute(ExecContext *xc, Trace::InstRecord *traceData) const
 {
-    bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), iss);
-
-    if (hypTrap) {
-        return std::make_shared<HypervisorTrap>(machInst, iss,
-                                                EC_TRAPPED_CP15_MCR_MRC);
-    } else {
-        return NoFault;
-    }
+    return mcrMrc15Trap(miscReg, machInst, xc->tcBase(), iss);
 }
 
 std::string
@@ -388,11 +381,9 @@ McrMrcImplDefined::McrMrcImplDefined(const char *_mnemonic,
 Fault
 McrMrcImplDefined::execute(ExecContext *xc, Trace::InstRecord *traceData) const
 {
-    bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), iss);
-
-    if (hypTrap) {
-        return std::make_shared<HypervisorTrap>(machInst, iss,
-                                                EC_TRAPPED_CP15_MCR_MRC);
+    Fault fault = mcrMrc15Trap(miscReg, machInst, xc->tcBase(), iss);
+    if (fault != NoFault) {
+        return fault;
     } else {
         return std::make_shared<UndefinedInstruction>(machInst, false,
                                                       mnemonic);
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index 7253f858f2..c5ab3fa20d 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -1,6 +1,6 @@
 // -*- mode:c++ -*-
 
-// Copyright (c) 2010-2013,2017-2020 ARM Limited
+// Copyright (c) 2010-2013,2017-2021 Arm Limited
 // All rights reserved
 //
 // The license below extends only to copyright in the software and shall
@@ -1115,7 +1115,7 @@ let {{
         MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
             RegId(MiscRegClass, preFlatDest)).index();
 
-        bool hypTrap = mcrMrc15TrapToHyp(miscReg, xc->tcBase(), imm);
+        Fault fault = mcrMrc15Trap(miscReg, machInst, xc->tcBase(), imm);
 
         auto [can_write, undefined] = canWriteCoprocReg(miscReg, Scr, Cpsr,
                                                         xc->tcBase());
@@ -1123,14 +1123,13 @@ let {{
         // if we're in non secure PL1 mode then we can trap regardless
         // of whether the register is accessible, in other modes we
         // trap if only if the register IS accessible.
-        if (undefined || (!can_write & !(hypTrap & !inUserMode(Cpsr) &
+        if (undefined || (!can_write && !(fault != NoFault && !inUserMode(Cpsr) &&
                                          !isSecure(xc->tcBase())))) {
             return std::make_shared<UndefinedInstruction>(machInst, false,
                                                           mnemonic);
         }
-        if (hypTrap) {
-            return std::make_shared<HypervisorTrap>(machInst, imm,
-                                                    EC_TRAPPED_CP15_MCR_MRC);
+        if (fault != NoFault) {
+            return fault;
         }
     '''