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arch-riscv: Fix a typo in fsgnjn_s decoder

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Negating the register value before unboxing to float32 will
generally result in a canonical 32-bit NaN (without the sign
bit set) so the result was incorrect in many cases.

Change-Id: I0c1bb3aadfca135ab0cc5ba1b58fc83d71fd300c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57069
Reviewed-by: Alex Richardson <alexrichardson@google.com>
Reviewed-by: Gabe Black <gabe.black@gmail.com>
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Luming Wang <wlm199558@126.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
ksco
2022-02-23 21:49:12 +08:00
parent 3ba623d673
commit 0eff31e564
1 changed files with 10 additions and 7 deletions
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17
src/arch/riscv/isa/decoder.isa
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@@ -1025,17 +1025,20 @@ decode QUADRANT default Unknown::unknown() {
}}, FloatDivOp);
0x10: decode ROUND_MODE {
0x0: fsgnj_s({{
Fd_bits = boxF32(insertBits(unboxF32(Fs2_bits), 30, 0,
unboxF32(Fs1_bits)));
auto sign = bits(unboxF32(Fs2_bits), 31);
Fd_bits = boxF32(insertBits(unboxF32(Fs1_bits), 31,
sign));
}}, FloatMiscOp);
0x1: fsgnjn_s({{
Fd_bits = boxF32(insertBits(unboxF32(~Fs2_bits), 30, 0,
unboxF32(Fs1_bits)));
auto sign = ~bits(unboxF32(Fs2_bits), 31);
Fd_bits = boxF32(insertBits(unboxF32(Fs1_bits), 31,
sign));
}}, FloatMiscOp);
0x2: fsgnjx_s({{
Fd_bits = boxF32(insertBits(
unboxF32(Fs1_bits) ^ unboxF32(Fs2_bits),
30, 0, unboxF32(Fs1_bits)));
auto sign = bits(
unboxF32(Fs1_bits) ^ unboxF32(Fs2_bits), 31);
Fd_bits = boxF32(insertBits(unboxF32(Fs1_bits), 31,
sign));
}}, FloatMiscOp);
}
0x11: decode ROUND_MODE {