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arch: Consolidate all the make_constructor methods in the ISA parser.

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These methods were all identical, except that IntRegOperand and
CCRegOperand classes had logic to handle operand predication. Since the
other operand types won't have predicates set, we can use the superset
version, and the other types will reduce to what they used to in
practice.

Change-Id: I51eeedcacb7cfc6e2c136742701ee9bf80ec4e15
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49721
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-08-20 22:11:11 -07:00
parent 6de0156cf7
commit 81d2f9f10a
1 changed files with 3 additions and 75 deletions
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78
src/arch/isa_parser/operand_types.py
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@@ -153,9 +153,6 @@ class RegOperand(Operand):
def isReg(self):
return 1
class IntRegOperand(RegOperand):
reg_class = 'IntRegClass'
def makeConstructor(self, predRead, predWrite):
c_src = ''
c_dest = ''
@@ -175,6 +172,9 @@ class IntRegOperand(RegOperand):
return c_src + c_dest
class IntRegOperand(RegOperand):
reg_class = 'IntRegClass'
def makeRead(self, predRead):
if (self.ctype == 'float' or self.ctype == 'double'):
error('Attempt to read integer register as FP')
@@ -222,19 +222,6 @@ class IntRegOperand(RegOperand):
class FloatRegOperand(RegOperand):
reg_class = 'FloatRegClass'
def makeConstructor(self, predRead, predWrite):
c_src = ''
c_dest = ''
if self.is_src:
c_src = self.src_reg_constructor % (self.reg_class, self.reg_spec)
if self.is_dest:
c_dest = self.dst_reg_constructor % (self.reg_class, self.reg_spec)
c_dest += f'\n\t_numTypedDestRegs[{self.reg_class}]++;'
return c_src + c_dest
def makeRead(self, predRead):
if self.read_code != None:
return self.buildReadCode(predRead, 'getRegOperand')
@@ -304,19 +291,6 @@ class VecRegOperand(RegOperand):
else:
return ''
def makeConstructor(self, predRead, predWrite):
c_src = ''
c_dest = ''
if self.is_src:
c_src = self.src_reg_constructor % (self.reg_class, self.reg_spec)
if self.is_dest:
c_dest = self.dst_reg_constructor % (self.reg_class, self.reg_spec)
c_dest += f'\n\t_numTypedDestRegs[{self.reg_class}]++;'
return c_src + c_dest
# Read destination register to write
def makeReadWElem(self, elem_op):
(elem_name, elem_ext) = elem_op
@@ -426,20 +400,6 @@ class VecElemOperand(RegOperand):
else:
return ''
def makeConstructor(self, predRead, predWrite):
c_src = ''
c_dest = ''
if self.is_src:
c_src = ('\n\tsetSrcRegIdx(_numSrcRegs++, RegId(%s, %s));' %
(self.reg_class, self.reg_spec))
if self.is_dest:
c_dest = ('\n\tsetDestRegIdx(_numDestRegs++, RegId(%s, %s));' %
(self.reg_class, self.reg_spec))
c_dest += f'\n\t_numTypedDestRegs[{self.reg_class}]++;'
return c_src + c_dest
def makeRead(self, predRead):
c_read = f'xc->getRegOperand(this, {self.src_reg_idx})'
@@ -464,19 +424,6 @@ class VecPredRegOperand(RegOperand):
def makeDecl(self):
return ''
def makeConstructor(self, predRead, predWrite):
c_src = ''
c_dest = ''
if self.is_src:
c_src = self.src_reg_constructor % (self.reg_class, self.reg_spec)
if self.is_dest:
c_dest = self.dst_reg_constructor % (self.reg_class, self.reg_spec)
c_dest += f'\n\t_numTypedDestRegs[{self.reg_class}]++;'
return c_src + c_dest
def makeRead(self, predRead):
func = 'getRegOperand'
if self.read_code != None:
@@ -535,25 +482,6 @@ class VecPredRegOperand(RegOperand):
class CCRegOperand(RegOperand):
reg_class = 'CCRegClass'
def makeConstructor(self, predRead, predWrite):
c_src = ''
c_dest = ''
if self.is_src:
c_src = self.src_reg_constructor % (self.reg_class, self.reg_spec)
if self.hasReadPred():
c_src = '\n\tif (%s) {%s\n\t}' % \
(self.read_predicate, c_src)
if self.is_dest:
c_dest = self.dst_reg_constructor % (self.reg_class, self.reg_spec)
c_dest += f'\n\t_numTypedDestRegs[{self.reg_class}]++;'
if self.hasWritePred():
c_dest = '\n\tif (%s) {%s\n\t}' % \
(self.write_predicate, c_dest)
return c_src + c_dest
def makeRead(self, predRead):
if (self.ctype == 'float' or self.ctype == 'double'):
error('Attempt to read condition-code register as FP')