arch-sparc: Use the OperandDesc classes in the ISA description.
Change-Id: I784ece5697c3b161a94f3eacbc3d175a1434ae2e Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49732 Maintainer: Gabe Black <gabe.black@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Boris Shingarov <shingarov@labware.com>
This commit is contained in:
Gabe Black
@@ -70,123 +70,130 @@ def operands {{
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# For clarity, descriptions that depend on unsigned behavior should
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# explicitly specify '.uq'.
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'Rd': ('IntReg', 'udw', 'RD', 'IsInteger', 1),
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'Rd': IntRegOp('udw', 'RD', 'IsInteger', 1),
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# The Rd from the previous window
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'Rd_prev': ('IntReg', 'udw', 'RD + NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 2),
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'Rd_prev': IntRegOp('udw',
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'RD + NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 2),
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# The Rd from the next window
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'Rd_next': ('IntReg', 'udw', 'RD + 2 * NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 3),
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'Rd_next': IntRegOp('udw',
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'RD + 2 * NumIntArchRegs + NumMicroIntRegs', 'IsInteger', 3),
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# For microcoded twin load instructions, RdTwin appears in the "code"
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# for the instruction is replaced by RdLow or RdHigh by the format
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# before it's processed by the iop.
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# The low (even) register of a two register pair
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'RdLow': ('IntReg', 'udw', 'RD & (~1)', 'IsInteger', 4),
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'RdLow': IntRegOp('udw', 'RD & (~1)', 'IsInteger', 4),
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# The high (odd) register of a two register pair
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'RdHigh': ('IntReg', 'udw', 'RD | 1', 'IsInteger', 5),
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'Rs1': ('IntReg', 'udw', 'RS1', 'IsInteger', 6),
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'Rs2': ('IntReg', 'udw', 'RS2', 'IsInteger', 7),
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'RdHigh': IntRegOp('udw', 'RD | 1', 'IsInteger', 5),
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'Rs1': IntRegOp('udw', 'RS1', 'IsInteger', 6),
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'Rs2': IntRegOp('udw', 'RS2', 'IsInteger', 7),
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# A microcode register. Right now, this is the only one.
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'uReg0': ('IntReg', 'udw', 'INTREG_UREG0', 'IsInteger', 8),
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'uReg0': IntRegOp('udw', 'INTREG_UREG0', 'IsInteger', 8),
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# Because double and quad precision register numbers are decoded
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# differently, they get different operands. The single precision versions
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# have an s post pended to their name.
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'Frds': ('FloatReg', 'sf', 'RD', 'IsFloating', 10),
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#'Frd': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
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'Frd_low': ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10),
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'Frd_high': ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10),
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'Frds': FloatRegOp('sf', 'RD', 'IsFloating', 10),
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#'Frd': FloatRegOp('df', 'dfpr(RD)', 'IsFloating', 10),
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'Frd_low': FloatRegOp('uw', 'dfprl(RD)', 'IsFloating', 10),
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'Frd_high': FloatRegOp('uw', 'dfprh(RD)', 'IsFloating', 10),
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# Each Frd_N refers to the Nth double precision register from Frd.
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# Note that this adds twice N to the register number.
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#'Frd_0': ('FloatReg', 'df', 'dfpr(RD)', 'IsFloating', 10),
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'Frd_0_low': ('FloatReg', 'uw', 'dfprl(RD)', 'IsFloating', 10),
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'Frd_0_high': ('FloatReg', 'uw', 'dfprh(RD)', 'IsFloating', 10),
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#'Frd_1': ('FloatReg', 'df', 'dfpr(RD) + 2', 'IsFloating', 10),
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'Frd_1_low': ('FloatReg', 'uw', 'dfprl(RD) + 2', 'IsFloating', 10),
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'Frd_1_high': ('FloatReg', 'uw', 'dfprh(RD) + 2', 'IsFloating', 10),
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#'Frd_2': ('FloatReg', 'df', 'dfpr(RD) + 4', 'IsFloating', 10),
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'Frd_2_low': ('FloatReg', 'uw', 'dfprl(RD) + 4', 'IsFloating', 10),
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'Frd_2_high': ('FloatReg', 'uw', 'dfprh(RD) + 4', 'IsFloating', 10),
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#'Frd_3': ('FloatReg', 'df', 'dfpr(RD) + 6', 'IsFloating', 10),
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'Frd_3_low': ('FloatReg', 'uw', 'dfprl(RD) + 6', 'IsFloating', 10),
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'Frd_3_high': ('FloatReg', 'uw', 'dfprh(RD) + 6', 'IsFloating', 10),
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#'Frd_4': ('FloatReg', 'df', 'dfpr(RD) + 8', 'IsFloating', 10),
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'Frd_4_low': ('FloatReg', 'uw', 'dfprl(RD) + 8', 'IsFloating', 10),
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'Frd_4_high': ('FloatReg', 'uw', 'dfprh(RD) + 8', 'IsFloating', 10),
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#'Frd_5': ('FloatReg', 'df', 'dfpr(RD) + 10', 'IsFloating', 10),
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'Frd_5_low': ('FloatReg', 'uw', 'dfprl(RD) + 10', 'IsFloating', 10),
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'Frd_5_high': ('FloatReg', 'uw', 'dfprh(RD) + 10', 'IsFloating', 10),
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#'Frd_6': ('FloatReg', 'df', 'dfpr(RD) + 12', 'IsFloating', 10),
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'Frd_6_low': ('FloatReg', 'uw', 'dfprl(RD) + 12', 'IsFloating', 10),
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'Frd_6_high': ('FloatReg', 'uw', 'dfprh(RD) + 12', 'IsFloating', 10),
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#'Frd_7': ('FloatReg', 'df', 'dfpr(RD) + 14', 'IsFloating', 10),
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'Frd_7_low': ('FloatReg', 'uw', 'dfprl(RD) + 14', 'IsFloating', 10),
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'Frd_7_high': ('FloatReg', 'uw', 'dfprh(RD) + 14', 'IsFloating', 10),
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'Frs1s': ('FloatReg', 'sf', 'RS1', 'IsFloating', 11),
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#'Frs1': ('FloatReg', 'df', 'dfpr(RS1)', 'IsFloating', 11),
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'Frs1_low': ('FloatReg', 'uw', 'dfprl(RS1)', 'IsFloating', 11),
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'Frs1_high': ('FloatReg', 'uw', 'dfprh(RS1)', 'IsFloating', 11),
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'Frs2s': ('FloatReg', 'sf', 'RS2', 'IsFloating', 12),
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#'Frs2': ('FloatReg', 'df', 'dfpr(RS2)', 'IsFloating', 12),
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'Frs2_low': ('FloatReg', 'uw', 'dfprl(RS2)', 'IsFloating', 12),
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'Frs2_high': ('FloatReg', 'uw', 'dfprh(RS2)', 'IsFloating', 12),
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'PC': ('PCState', 'udw', 'pc', (None, None, 'IsControl'), 30),
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'NPC': ('PCState', 'udw', 'npc', (None, None, 'IsControl'), 30),
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'NNPC': ('PCState', 'udw', 'nnpc', (None, None, 'IsControl'), 30),
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#'Frd_0': FloatRegOp('df', 'dfpr(RD)', 'IsFloating', 10),
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'Frd_0_low': FloatRegOp('uw', 'dfprl(RD)', 'IsFloating', 10),
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'Frd_0_high': FloatRegOp('uw', 'dfprh(RD)', 'IsFloating', 10),
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#'Frd_1': FloatRegOp('df', 'dfpr(RD) + 2', 'IsFloating', 10),
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'Frd_1_low': FloatRegOp('uw', 'dfprl(RD) + 2', 'IsFloating', 10),
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'Frd_1_high': FloatRegOp('uw', 'dfprh(RD) + 2', 'IsFloating', 10),
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#'Frd_2': FloatRegOp('df', 'dfpr(RD) + 4', 'IsFloating', 10),
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'Frd_2_low': FloatRegOp('uw', 'dfprl(RD) + 4', 'IsFloating', 10),
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'Frd_2_high': FloatRegOp('uw', 'dfprh(RD) + 4', 'IsFloating', 10),
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#'Frd_3': FloatRegOp('df', 'dfpr(RD) + 6', 'IsFloating', 10),
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'Frd_3_low': FloatRegOp('uw', 'dfprl(RD) + 6', 'IsFloating', 10),
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'Frd_3_high': FloatRegOp('uw', 'dfprh(RD) + 6', 'IsFloating', 10),
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#'Frd_4': FloatRegOp('df', 'dfpr(RD) + 8', 'IsFloating', 10),
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'Frd_4_low': FloatRegOp('uw', 'dfprl(RD) + 8', 'IsFloating', 10),
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'Frd_4_high': FloatRegOp('uw', 'dfprh(RD) + 8', 'IsFloating', 10),
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#'Frd_5': FloatRegOp('df', 'dfpr(RD) + 10', 'IsFloating', 10),
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'Frd_5_low': FloatRegOp('uw', 'dfprl(RD) + 10', 'IsFloating', 10),
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'Frd_5_high': FloatRegOp('uw', 'dfprh(RD) + 10', 'IsFloating', 10),
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#'Frd_6': FloatRegOp('df', 'dfpr(RD) + 12', 'IsFloating', 10),
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'Frd_6_low': FloatRegOp('uw', 'dfprl(RD) + 12', 'IsFloating', 10),
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'Frd_6_high': FloatRegOp('uw', 'dfprh(RD) + 12', 'IsFloating', 10),
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#'Frd_7': FloatRegOp('df', 'dfpr(RD) + 14', 'IsFloating', 10),
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'Frd_7_low': FloatRegOp('uw', 'dfprl(RD) + 14', 'IsFloating', 10),
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'Frd_7_high': FloatRegOp('uw', 'dfprh(RD) + 14', 'IsFloating', 10),
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'Frs1s': FloatRegOp('sf', 'RS1', 'IsFloating', 11),
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#'Frs1': FloatRegOp('df', 'dfpr(RS1)', 'IsFloating', 11),
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'Frs1_low': FloatRegOp('uw', 'dfprl(RS1)', 'IsFloating', 11),
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'Frs1_high': FloatRegOp('uw', 'dfprh(RS1)', 'IsFloating', 11),
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'Frs2s': FloatRegOp('sf', 'RS2', 'IsFloating', 12),
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#'Frs2': FloatRegOp('df', 'dfpr(RS2)', 'IsFloating', 12),
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'Frs2_low': FloatRegOp('uw', 'dfprl(RS2)', 'IsFloating', 12),
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'Frs2_high': FloatRegOp('uw', 'dfprh(RS2)', 'IsFloating', 12),
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'PC': PCStateOp('udw', 'pc', (None, None, 'IsControl'), 30),
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'NPC': PCStateOp('udw', 'npc', (None, None, 'IsControl'), 30),
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'NNPC': PCStateOp('udw', 'nnpc',
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(None, None, 'IsControl'), 30),
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# Registers which are used explicitly in instructions
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'R0': ('IntReg', 'udw', '0', None, 6),
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'R1': ('IntReg', 'udw', '1', None, 7),
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'R15': ('IntReg', 'udw', '15', 'IsInteger', 8),
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'R16': ('IntReg', 'udw', '16', None, 9),
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'O0': ('IntReg', 'udw', 'INTREG_O0', 'IsInteger', 10),
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'O1': ('IntReg', 'udw', 'INTREG_O1', 'IsInteger', 11),
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'O2': ('IntReg', 'udw', 'INTREG_O2', 'IsInteger', 12),
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'O3': ('IntReg', 'udw', 'INTREG_O3', 'IsInteger', 13),
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'O4': ('IntReg', 'udw', 'INTREG_O4', 'IsInteger', 14),
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'O5': ('IntReg', 'udw', 'INTREG_O5', 'IsInteger', 15),
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'R0': IntRegOp('udw', '0', None, 6),
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'R1': IntRegOp('udw', '1', None, 7),
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'R15': IntRegOp('udw', '15', 'IsInteger', 8),
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'R16': IntRegOp('udw', '16', None, 9),
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'O0': IntRegOp('udw', 'INTREG_O0', 'IsInteger', 10),
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'O1': IntRegOp('udw', 'INTREG_O1', 'IsInteger', 11),
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'O2': IntRegOp('udw', 'INTREG_O2', 'IsInteger', 12),
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'O3': IntRegOp('udw', 'INTREG_O3', 'IsInteger', 13),
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'O4': IntRegOp('udw', 'INTREG_O4', 'IsInteger', 14),
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'O5': IntRegOp('udw', 'INTREG_O5', 'IsInteger', 15),
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# Control registers
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'Y': ('IntReg', 'udw', 'INTREG_Y', None, 40),
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'Ccr': ('IntReg', 'udw', 'INTREG_CCR', None, 41),
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'Asi': ('ControlReg', 'udw', 'MISCREG_ASI', None, 42),
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'Fprs': ('ControlReg', 'udw', 'MISCREG_FPRS', None, 43),
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'Pcr': ('ControlReg', 'udw', 'MISCREG_PCR', None, 44),
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'Pic': ('ControlReg', 'udw', 'MISCREG_PIC', None, 45),
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'Gsr': ('IntReg', 'udw', 'INTREG_GSR', None, 46),
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'Softint': ('ControlReg', 'udw', 'MISCREG_SOFTINT', None, 47),
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'SoftintSet': ('ControlReg', 'udw', 'MISCREG_SOFTINT_SET', None, 48),
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'SoftintClr': ('ControlReg', 'udw', 'MISCREG_SOFTINT_CLR', None, 49),
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'TickCmpr': ('ControlReg', 'udw', 'MISCREG_TICK_CMPR', None, 50),
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'Stick': ('ControlReg', 'udw', 'MISCREG_STICK', None, 51),
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'StickCmpr': ('ControlReg', 'udw', 'MISCREG_STICK_CMPR', None, 52),
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'Y': IntRegOp('udw', 'INTREG_Y', None, 40),
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'Ccr': IntRegOp('udw', 'INTREG_CCR', None, 41),
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'Asi': ControlRegOp('udw', 'MISCREG_ASI', None, 42),
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'Fprs': ControlRegOp('udw', 'MISCREG_FPRS', None, 43),
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'Pcr': ControlRegOp('udw', 'MISCREG_PCR', None, 44),
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'Pic': ControlRegOp('udw', 'MISCREG_PIC', None, 45),
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'Gsr': IntRegOp('udw', 'INTREG_GSR', None, 46),
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'Softint': ControlRegOp('udw', 'MISCREG_SOFTINT', None, 47),
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'SoftintSet': ControlRegOp('udw', 'MISCREG_SOFTINT_SET', None, 48),
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'SoftintClr': ControlRegOp('udw', 'MISCREG_SOFTINT_CLR', None, 49),
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'TickCmpr': ControlRegOp('udw', 'MISCREG_TICK_CMPR', None, 50),
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'Stick': ControlRegOp('udw', 'MISCREG_STICK', None, 51),
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'StickCmpr': ControlRegOp('udw', 'MISCREG_STICK_CMPR', None, 52),
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'Tpc': ('ControlReg', 'udw', 'MISCREG_TPC', None, 53),
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'Tnpc': ('ControlReg', 'udw', 'MISCREG_TNPC', None, 54),
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'Tstate': ('ControlReg', 'udw', 'MISCREG_TSTATE', None, 55),
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'Tt': ('ControlReg', 'udw', 'MISCREG_TT', None, 56),
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'Tick': ('ControlReg', 'udw', 'MISCREG_TICK', None, 57),
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'Tba': ('ControlReg', 'udw', 'MISCREG_TBA', None, 58),
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'Pstate': ('ControlReg', 'pstate', 'MISCREG_PSTATE', None, 59),
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'Tl': ('ControlReg', 'udw', 'MISCREG_TL', None, 60),
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'Pil': ('ControlReg', 'udw', 'MISCREG_PIL', None, 61),
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'Cwp': ('ControlReg', 'udw', 'MISCREG_CWP',
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'Tpc': ControlRegOp('udw', 'MISCREG_TPC', None, 53),
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'Tnpc': ControlRegOp('udw', 'MISCREG_TNPC', None, 54),
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'Tstate': ControlRegOp('udw', 'MISCREG_TSTATE', None, 55),
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'Tt': ControlRegOp('udw', 'MISCREG_TT', None, 56),
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'Tick': ControlRegOp('udw', 'MISCREG_TICK', None, 57),
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'Tba': ControlRegOp('udw', 'MISCREG_TBA', None, 58),
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'Pstate': ControlRegOp('pstate', 'MISCREG_PSTATE', None, 59),
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'Tl': ControlRegOp('udw', 'MISCREG_TL', None, 60),
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'Pil': ControlRegOp('udw', 'MISCREG_PIL', None, 61),
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'Cwp': ControlRegOp('udw', 'MISCREG_CWP',
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(None, None, ['IsSerializeAfter',
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'IsSerializing',
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'IsNonSpeculative']), 62),
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'Cansave': ('IntReg', 'udw', 'INTREG_CANSAVE', None, 63),
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'Canrestore': ('IntReg', 'udw', 'INTREG_CANRESTORE', None, 64),
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'Cleanwin': ('IntReg', 'udw', 'INTREG_CLEANWIN', None, 65),
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'Otherwin': ('IntReg', 'udw', 'INTREG_OTHERWIN', None, 66),
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'Wstate': ('IntReg', 'udw', 'INTREG_WSTATE', None, 67),
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'Gl': ('ControlReg', 'udw', 'MISCREG_GL', None, 68),
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'Cansave': IntRegOp('udw', 'INTREG_CANSAVE', None, 63),
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'Canrestore': IntRegOp('udw', 'INTREG_CANRESTORE', None, 64),
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'Cleanwin': IntRegOp('udw', 'INTREG_CLEANWIN', None, 65),
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'Otherwin': IntRegOp('udw', 'INTREG_OTHERWIN', None, 66),
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'Wstate': IntRegOp('udw', 'INTREG_WSTATE', None, 67),
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'Gl': ControlRegOp('udw', 'MISCREG_GL', None, 68),
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'Hpstate': ('ControlReg', 'hpstate', 'MISCREG_HPSTATE', None, 69),
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'Htstate': ('ControlReg', 'udw', 'MISCREG_HTSTATE', None, 70),
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'Hintp': ('ControlReg', 'udw', 'MISCREG_HINTP', None, 71),
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'Htba': ('ControlReg', 'udw', 'MISCREG_HTBA', None, 72),
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'HstickCmpr': ('ControlReg', 'udw', 'MISCREG_HSTICK_CMPR', None, 73),
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'Hver': ('ControlReg', 'udw', 'MISCREG_HVER', None, 74),
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'StrandStsReg': ('ControlReg', 'udw', 'MISCREG_STRAND_STS_REG', None, 75),
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'Hpstate': ControlRegOp('hpstate', 'MISCREG_HPSTATE', None, 69),
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'Htstate': ControlRegOp('udw', 'MISCREG_HTSTATE', None, 70),
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'Hintp': ControlRegOp('udw', 'MISCREG_HINTP', None, 71),
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'Htba': ControlRegOp('udw', 'MISCREG_HTBA', None, 72),
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'HstickCmpr': ControlRegOp('udw', 'MISCREG_HSTICK_CMPR', None, 73),
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'Hver': ControlRegOp('udw', 'MISCREG_HVER', None, 74),
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'StrandStsReg': ControlRegOp('udw', 'MISCREG_STRAND_STS_REG',
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None, 75),
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'Fsr': ('ControlReg', 'udw', 'MISCREG_FSR', (None, None, ['IsSerializeAfter','IsSerializing','IsNonSpeculative']), 80),
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'Fsr': ControlRegOp('udw', 'MISCREG_FSR',
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(None, None, ['IsSerializeAfter',
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'IsSerializing',
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'IsNonSpeculative']), 80),
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# Mem gets a large number so it's always last
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'Mem': ('Mem', 'udw', None, (None, 'IsLoad', 'IsStore'), 100)
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'Mem': MemOp('udw', None, (None, 'IsLoad', 'IsStore'), 100)
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}};
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