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arch,cpu: Replace num${Type}DestReg accessors with numDestReg(type).

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Change-Id: I32be58cce831c8c7d5b9e3d3f49f428a06c722a2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49713
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-08-20 19:43:38 -07:00
parent 967bada8db
commit a5ab19d3ef
4 changed files with 14 additions and 48 deletions
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6
src/arch/isa_parser/operand_list.py
View File

@@ -116,12 +116,6 @@ class OperandList(object):
self.numSrcRegs = len(srcs)
self.numDestRegs = len(dests)
self.numFPDestRegs = sum(r.isFloatReg() for r in dests)
self.numIntDestRegs = sum(r.isIntReg() for r in dests)
self.numVecDestRegs = sum(r.isVecReg() for r in dests)
self.numVecPredDestRegs = sum(r.isVecPredReg() for r in dests)
self.numCCDestRegs = sum(r.isCCReg() for r in dests)
self.numMiscDestRegs = sum(r.isControlReg() for r in dests)
if len(mem) > 1:
error("Code block has more than one memory operand")

17
src/cpu/o3/dyn_inst.hh
View File

@@ -680,21 +680,10 @@ class DynInst : public ExecContext, public RefCounted
/** Returns the number of destination registers. */
size_t numDestRegs() const { return numDests(); }
// the following are used to track physical register usage
// for machines with separate int & FP reg files
int8_t numFPDestRegs() const { return staticInst->numFPDestRegs(); }
int8_t numIntDestRegs() const { return staticInst->numIntDestRegs(); }
int8_t numCCDestRegs() const { return staticInst->numCCDestRegs(); }
int8_t numVecDestRegs() const { return staticInst->numVecDestRegs(); }
int8_t
numVecElemDestRegs() const
size_t
numDestRegs(RegClassType type) const
{
return staticInst->numVecElemDestRegs();
}
int8_t
numVecPredDestRegs() const
{
return staticInst->numVecPredDestRegs();
return staticInst->numDestRegs(type);
}
/** Returns the logical register index of the i'th destination register. */

12
src/cpu/o3/rename.cc
View File

@@ -656,12 +656,12 @@ Rename::renameInsts(ThreadID tid)
// Check here to make sure there are enough destination registers
// to rename to. Otherwise block.
if (!renameMap[tid]->canRename(inst->numIntDestRegs(),
inst->numFPDestRegs(),
inst->numVecDestRegs(),
inst->numVecElemDestRegs(),
inst->numVecPredDestRegs(),
inst->numCCDestRegs())) {
if (!renameMap[tid]->canRename(inst->numDestRegs(IntRegClass),
inst->numDestRegs(FloatRegClass),
inst->numDestRegs(VecRegClass),
inst->numDestRegs(VecElemClass),
inst->numDestRegs(VecPredRegClass),
inst->numDestRegs(CCRegClass))) {
DPRINTF(Rename,
"Blocking due to "
" lack of free physical registers to rename to.\n");

27
src/cpu/static_inst.hh
View File

@@ -115,36 +115,19 @@ class StaticInst : public RefCounted, public StaticInstFlags
public:
/// @name Register information.
/// The sum of numFPDestRegs(), numIntDestRegs(), numVecDestRegs(),
/// numVecElemDestRegs() and numVecPredDestRegs() equals numDestRegs().
/// The former two functions are used to track physical register usage for
/// machines with separate int & FP reg files, the next three are for
/// machines with vector and predicate register files.
/// The sum of the different numDestRegs([type])-s equals numDestRegs().
/// The per-type function is used to track physical register usage.
//@{
/// Number of source registers.
uint8_t numSrcRegs() const { return _numSrcRegs; }
/// Number of destination registers.
uint8_t numDestRegs() const { return _numDestRegs; }
/// Number of floating-point destination regs.
uint8_t numFPDestRegs() const { return _numTypedDestRegs[FloatRegClass]; }
/// Number of integer destination regs.
uint8_t numIntDestRegs() const { return _numTypedDestRegs[IntRegClass]; }
/// Number of vector destination regs.
uint8_t numVecDestRegs() const { return _numTypedDestRegs[VecRegClass]; }
/// Number of vector element destination regs.
/// Number of destination registers of a particular type.
uint8_t
numVecElemDestRegs() const
numDestRegs(RegClassType type) const
{
return _numTypedDestRegs[VecElemClass];
return _numTypedDestRegs[type];
}
/// Number of predicate destination regs.
uint8_t
numVecPredDestRegs() const
{
return _numTypedDestRegs[VecPredRegClass];
}
/// Number of coprocesor destination regs.
uint8_t numCCDestRegs() const { return _numTypedDestRegs[CCRegClass]; }
//@}
/// @name Flag accessors.