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cpu: Remove the default implementation of (get|set)RegFlat.

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This was originally intended to call back into the original readIntReg,
setIntReg, etc, but now that *those* are implemented by calling into
getRegFlat, setRegFlat, etc, that's a circular dependency and makes that
implementation unusable.

Change-Id: I4135f0d8721f5f9d724be590767bed0023a9de20
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49698
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-08-11 01:40:11 -07:00
parent ae10990287
commit 40b9c0d2bd
2 changed files with 3 additions and 80 deletions
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77
src/cpu/thread_context.cc
View File

@@ -197,83 +197,6 @@ ThreadContext::setRegFlat(const RegId &reg, RegVal val)
setRegFlat(reg, &val);
}
void
ThreadContext::getRegFlat(const RegId &reg, void *val) const
{
const RegIndex idx = reg.index();
const RegClassType type = reg.classValue();
switch (type) {
case IntRegClass:
*(RegVal *)val = readIntRegFlat(idx);
break;
case FloatRegClass:
*(RegVal *)val = readFloatRegFlat(idx);
break;
case VecRegClass:
*(TheISA::VecRegContainer *)val = readVecRegFlat(idx);
break;
case VecElemClass:
*(RegVal *)val = readVecElemFlat(idx);
break;
case VecPredRegClass:
*(TheISA::VecPredRegContainer *)val = readVecPredRegFlat(idx);
break;
case CCRegClass:
*(RegVal *)val = readCCRegFlat(idx);
break;
case MiscRegClass:
panic("MiscRegs should not be read with getReg.");
default:
panic("Unrecognized register class type %d.", type);
}
}
void *
ThreadContext::getWritableRegFlat(const RegId &reg)
{
const RegIndex idx = reg.index();
const RegClassType type = reg.classValue();
switch (type) {
case VecRegClass:
return &getWritableVecRegFlat(idx);
case VecPredRegClass:
return &getWritableVecPredRegFlat(idx);
default:
panic("Unrecognized register class type %d.", type);
}
}
void
ThreadContext::setRegFlat(const RegId &reg, const void *val)
{
const RegIndex idx = reg.index();
const RegClassType type = reg.classValue();
switch (type) {
case IntRegClass:
setIntRegFlat(idx, *(RegVal *)val);
break;
case FloatRegClass:
setFloatRegFlat(idx, *(RegVal *)val);
break;
case VecRegClass:
setVecRegFlat(idx, *(TheISA::VecRegContainer *)val);
break;
case VecElemClass:
setVecElemFlat(idx, *(RegVal *)val);
break;
case VecPredRegClass:
setVecPredRegFlat(idx, *(TheISA::VecPredRegContainer *)val);
break;
case CCRegClass:
setCCRegFlat(idx, *(RegVal *)val);
break;
case MiscRegClass:
panic("MiscRegs should not be read with getReg.");
default:
panic("Unrecognized register class type %d.", type);
}
}
void
serialize(const ThreadContext &tc, CheckpointOut &cp)
{

6
src/cpu/thread_context.hh
View File

@@ -335,11 +335,11 @@ class ThreadContext : public PCEventScope
*/
virtual RegVal getRegFlat(const RegId &reg) const;
virtual void getRegFlat(const RegId &reg, void *val) const;
virtual void *getWritableRegFlat(const RegId &reg);
virtual void getRegFlat(const RegId &reg, void *val) const = 0;
virtual void *getWritableRegFlat(const RegId &reg) = 0;
virtual void setRegFlat(const RegId &reg, RegVal val);
virtual void setRegFlat(const RegId &reg, const void *val);
virtual void setRegFlat(const RegId &reg, const void *val) = 0;
RegVal
readIntRegFlat(RegIndex idx) const