From 40b9c0d2bdb492da6820459fdc2e0fbb9fa4cb1e Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 11 Aug 2021 01:40:11 -0700 Subject: [PATCH] cpu: Remove the default implementation of (get|set)RegFlat. This was originally intended to call back into the original readIntReg, setIntReg, etc, but now that *those* are implemented by calling into getRegFlat, setRegFlat, etc, that's a circular dependency and makes that implementation unusable. Change-Id: I4135f0d8721f5f9d724be590767bed0023a9de20 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49698 Reviewed-by: Giacomo Travaglini Maintainer: Giacomo Travaglini Tested-by: kokoro --- src/cpu/thread_context.cc | 77 --------------------------------------- src/cpu/thread_context.hh | 6 +-- 2 files changed, 3 insertions(+), 80 deletions(-) diff --git a/src/cpu/thread_context.cc b/src/cpu/thread_context.cc index 228f193259..181c583721 100644 --- a/src/cpu/thread_context.cc +++ b/src/cpu/thread_context.cc @@ -197,83 +197,6 @@ ThreadContext::setRegFlat(const RegId ®, RegVal val) setRegFlat(reg, &val); } -void -ThreadContext::getRegFlat(const RegId ®, void *val) const -{ - const RegIndex idx = reg.index(); - const RegClassType type = reg.classValue(); - switch (type) { - case IntRegClass: - *(RegVal *)val = readIntRegFlat(idx); - break; - case FloatRegClass: - *(RegVal *)val = readFloatRegFlat(idx); - break; - case VecRegClass: - *(TheISA::VecRegContainer *)val = readVecRegFlat(idx); - break; - case VecElemClass: - *(RegVal *)val = readVecElemFlat(idx); - break; - case VecPredRegClass: - *(TheISA::VecPredRegContainer *)val = readVecPredRegFlat(idx); - break; - case CCRegClass: - *(RegVal *)val = readCCRegFlat(idx); - break; - case MiscRegClass: - panic("MiscRegs should not be read with getReg."); - default: - panic("Unrecognized register class type %d.", type); - } -} - -void * -ThreadContext::getWritableRegFlat(const RegId ®) -{ - const RegIndex idx = reg.index(); - const RegClassType type = reg.classValue(); - switch (type) { - case VecRegClass: - return &getWritableVecRegFlat(idx); - case VecPredRegClass: - return &getWritableVecPredRegFlat(idx); - default: - panic("Unrecognized register class type %d.", type); - } -} - -void -ThreadContext::setRegFlat(const RegId ®, const void *val) -{ - const RegIndex idx = reg.index(); - const RegClassType type = reg.classValue(); - switch (type) { - case IntRegClass: - setIntRegFlat(idx, *(RegVal *)val); - break; - case FloatRegClass: - setFloatRegFlat(idx, *(RegVal *)val); - break; - case VecRegClass: - setVecRegFlat(idx, *(TheISA::VecRegContainer *)val); - break; - case VecElemClass: - setVecElemFlat(idx, *(RegVal *)val); - break; - case VecPredRegClass: - setVecPredRegFlat(idx, *(TheISA::VecPredRegContainer *)val); - break; - case CCRegClass: - setCCRegFlat(idx, *(RegVal *)val); - break; - case MiscRegClass: - panic("MiscRegs should not be read with getReg."); - default: - panic("Unrecognized register class type %d.", type); - } -} - void serialize(const ThreadContext &tc, CheckpointOut &cp) { diff --git a/src/cpu/thread_context.hh b/src/cpu/thread_context.hh index 09cef3c156..5e1c5ad3cd 100644 --- a/src/cpu/thread_context.hh +++ b/src/cpu/thread_context.hh @@ -335,11 +335,11 @@ class ThreadContext : public PCEventScope */ virtual RegVal getRegFlat(const RegId ®) const; - virtual void getRegFlat(const RegId ®, void *val) const; - virtual void *getWritableRegFlat(const RegId ®); + virtual void getRegFlat(const RegId ®, void *val) const = 0; + virtual void *getWritableRegFlat(const RegId ®) = 0; virtual void setRegFlat(const RegId ®, RegVal val); - virtual void setRegFlat(const RegId ®, const void *val); + virtual void setRegFlat(const RegId ®, const void *val) = 0; RegVal readIntRegFlat(RegIndex idx) const