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cpu-o3: Print vec and vec pred reg values with valString.

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Remove the need for the VecRegContainer and VecPredRegContainer types.

Change-Id: If230449d7f43a5a9b7c3e00b2692cc35ce971c63
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49705
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-08-11 05:14:13 -07:00
parent 9950d58e16
commit b5edb3b0e4
1 changed files with 4 additions and 4 deletions
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8
src/cpu/o3/regfile.hh
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@@ -211,7 +211,7 @@ class PhysRegFile
case VecRegClass:
vectorRegFile.get(idx, val);
DPRINTF(IEW, "RegFile: Access to vector register %i, has "
"data %s\n", idx, *(TheISA::VecRegContainer *)val);
"data %s\n", idx, vectorRegFile.regClass.valString(val));
break;
case VecElemClass:
*(RegVal *)val = getReg(phys_reg);
@@ -219,7 +219,7 @@ class PhysRegFile
case VecPredRegClass:
vecPredRegFile.get(idx, val);
DPRINTF(IEW, "RegFile: Access to predicate register %i, has "
"data %s\n", idx, *(TheISA::VecRegContainer *)val);
"data %s\n", idx, vecPredRegFile.regClass.valString(val));
break;
case CCRegClass:
*(RegVal *)val = getReg(phys_reg);
@@ -293,7 +293,7 @@ class PhysRegFile
break;
case VecRegClass:
DPRINTF(IEW, "RegFile: Setting vector register %i to %s\n",
idx, *(TheISA::VecRegContainer *)val);
idx, vectorRegFile.regClass.valString(val));
vectorRegFile.set(idx, val);
break;
case VecElemClass:
@@ -301,7 +301,7 @@ class PhysRegFile
break;
case VecPredRegClass:
DPRINTF(IEW, "RegFile: Setting predicate register %i to %s\n",
idx, *(TheISA::VecRegContainer *)val);
idx, vectorRegFile.regClass.valString(val));
vecPredRegFile.set(idx, val);
break;
case CCRegClass: