From b5edb3b0e4853a2b1b6fd32cf27cd1f69baea392 Mon Sep 17 00:00:00 2001 From: Gabe Black Date: Wed, 11 Aug 2021 05:14:13 -0700 Subject: [PATCH] cpu-o3: Print vec and vec pred reg values with valString. Remove the need for the VecRegContainer and VecPredRegContainer types. Change-Id: If230449d7f43a5a9b7c3e00b2692cc35ce971c63 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49705 Reviewed-by: Giacomo Travaglini Maintainer: Giacomo Travaglini Tested-by: kokoro --- src/cpu/o3/regfile.hh | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh index 9cb8fc24d0..b5d972d3c5 100644 --- a/src/cpu/o3/regfile.hh +++ b/src/cpu/o3/regfile.hh @@ -211,7 +211,7 @@ class PhysRegFile case VecRegClass: vectorRegFile.get(idx, val); DPRINTF(IEW, "RegFile: Access to vector register %i, has " - "data %s\n", idx, *(TheISA::VecRegContainer *)val); + "data %s\n", idx, vectorRegFile.regClass.valString(val)); break; case VecElemClass: *(RegVal *)val = getReg(phys_reg); @@ -219,7 +219,7 @@ class PhysRegFile case VecPredRegClass: vecPredRegFile.get(idx, val); DPRINTF(IEW, "RegFile: Access to predicate register %i, has " - "data %s\n", idx, *(TheISA::VecRegContainer *)val); + "data %s\n", idx, vecPredRegFile.regClass.valString(val)); break; case CCRegClass: *(RegVal *)val = getReg(phys_reg); @@ -293,7 +293,7 @@ class PhysRegFile break; case VecRegClass: DPRINTF(IEW, "RegFile: Setting vector register %i to %s\n", - idx, *(TheISA::VecRegContainer *)val); + idx, vectorRegFile.regClass.valString(val)); vectorRegFile.set(idx, val); break; case VecElemClass: @@ -301,7 +301,7 @@ class PhysRegFile break; case VecPredRegClass: DPRINTF(IEW, "RegFile: Setting predicate register %i to %s\n", - idx, *(TheISA::VecRegContainer *)val); + idx, vectorRegFile.regClass.valString(val)); vecPredRegFile.set(idx, val); break; case CCRegClass: