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cpu: Remove VecRegContainer from ThreadContext::compare.

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Change-Id: I5a0f9d30fe56806d46fb54d62e1e58d02a319879
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49708
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-08-12 01:54:14 -07:00
parent b5edb3b0e4
commit 3e846d20ed
1 changed files with 11 additions and 5 deletions
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16
src/cpu/thread_context.cc
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@@ -83,13 +83,19 @@ ThreadContext::compare(ThreadContext *one, ThreadContext *two)
}
// Then loop through the vector registers.
for (int i = 0; i < regClasses.at(VecRegClass).numRegs(); ++i) {
const auto &vec_class = regClasses.at(VecRegClass);
std::vector<uint8_t> vec1(vec_class.regBytes());
std::vector<uint8_t> vec2(vec_class.regBytes());
for (int i = 0; i < vec_class.numRegs(); ++i) {
RegId rid(VecRegClass, i);
const TheISA::VecRegContainer& t1 = one->readVecReg(rid);
const TheISA::VecRegContainer& t2 = two->readVecReg(rid);
if (t1 != t2)
one->getReg(rid, vec1.data());
two->getReg(rid, vec2.data());
if (vec1 != vec2) {
panic("Vec reg idx %d doesn't match, one: %#x, two: %#x",
i, t1, t2);
i, vec_class.valString(vec1.data()),
vec_class.valString(vec2.data()));
}
}
// Then loop through the predicate registers.