cpu-simple: Ignore writes to the "zero" register.

Rather than constantly overwriting the "zero" register to return its
value to zero, just ignore writes to it.

We assume here that the "zero" register is a standard RegVal type
register (ie not bigger than 64 bits) and is accessed as such.

Change-Id: I06029b78103019c668647569c6037ca64a4d9c76
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49709
Maintainer: Gabe Black <gabe.black@gmail.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-08-14 01:28:45 -07:00
parent f12c330f40
commit aa4b6047e5
3 changed files with 6 additions and 4 deletions

View File

@@ -97,7 +97,6 @@ class ExecContext : public gem5::ExecContext
pcState(*inst->pc);
setPredicate(inst->readPredicate());
setMemAccPredicate(inst->readMemAccPredicate());
thread.setIntReg(zeroReg, 0);
}
~ExecContext()

View File

@@ -307,9 +307,6 @@ BaseSimpleCPU::preExecute()
SimpleExecContext &t_info = *threadInfo[curThread];
SimpleThread* thread = t_info.thread;
// maintain $r0 semantics
thread->setIntReg(zeroReg, 0);
// resets predicates
t_info.setPredicate(true);
t_info.setMemAccPredicate(true);

View File

@@ -405,6 +405,9 @@ class SimpleThread : public ThreadState, public ThreadContext
auto &reg_file = regFiles[reg.classValue()];
const auto &reg_class = reg_file.regClass;
if (reg.index() == reg_class.zeroReg())
return;
DPRINTFV(reg_class.debug(), "Setting %s register %s (%d) to %#x.\n",
reg.className(), reg_class.regName(arch_reg), idx, val);
reg_file.reg(idx) = val;
@@ -418,6 +421,9 @@ class SimpleThread : public ThreadState, public ThreadContext
auto &reg_file = regFiles[reg.classValue()];
const auto &reg_class = reg_file.regClass;
if (reg.index() == reg_class.zeroReg())
return;
DPRINTFV(reg_class.debug(), "Setting %s register %d to %#x.\n",
reg.className(), idx, val);
reg_file.reg(idx) = val;