cpu-simple: Ignore writes to the "zero" register.
Rather than constantly overwriting the "zero" register to return its value to zero, just ignore writes to it. We assume here that the "zero" register is a standard RegVal type register (ie not bigger than 64 bits) and is accessed as such. Change-Id: I06029b78103019c668647569c6037ca64a4d9c76 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49709 Maintainer: Gabe Black <gabe.black@gmail.com> Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
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@@ -97,7 +97,6 @@ class ExecContext : public gem5::ExecContext
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pcState(*inst->pc);
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setPredicate(inst->readPredicate());
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setMemAccPredicate(inst->readMemAccPredicate());
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thread.setIntReg(zeroReg, 0);
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}
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~ExecContext()
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@@ -307,9 +307,6 @@ BaseSimpleCPU::preExecute()
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SimpleExecContext &t_info = *threadInfo[curThread];
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SimpleThread* thread = t_info.thread;
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// maintain $r0 semantics
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thread->setIntReg(zeroReg, 0);
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// resets predicates
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t_info.setPredicate(true);
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t_info.setMemAccPredicate(true);
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@@ -405,6 +405,9 @@ class SimpleThread : public ThreadState, public ThreadContext
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auto ®_file = regFiles[reg.classValue()];
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const auto ®_class = reg_file.regClass;
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if (reg.index() == reg_class.zeroReg())
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return;
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DPRINTFV(reg_class.debug(), "Setting %s register %s (%d) to %#x.\n",
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reg.className(), reg_class.regName(arch_reg), idx, val);
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reg_file.reg(idx) = val;
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@@ -418,6 +421,9 @@ class SimpleThread : public ThreadState, public ThreadContext
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auto ®_file = regFiles[reg.classValue()];
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const auto ®_class = reg_file.regClass;
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if (reg.index() == reg_class.zeroReg())
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return;
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DPRINTFV(reg_class.debug(), "Setting %s register %d to %#x.\n",
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reg.className(), idx, val);
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reg_file.reg(idx) = val;
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