diff --git a/src/cpu/minor/exec_context.hh b/src/cpu/minor/exec_context.hh
index 0c01793acc..43dad2697c 100644
--- a/src/cpu/minor/exec_context.hh
+++ b/src/cpu/minor/exec_context.hh
@@ -97,7 +97,6 @@ class ExecContext : public gem5::ExecContext
         pcState(*inst->pc);
         setPredicate(inst->readPredicate());
         setMemAccPredicate(inst->readMemAccPredicate());
-        thread.setIntReg(zeroReg, 0);
     }
 
     ~ExecContext()
diff --git a/src/cpu/simple/base.cc b/src/cpu/simple/base.cc
index 4cc8e1fb80..6db8025965 100644
--- a/src/cpu/simple/base.cc
+++ b/src/cpu/simple/base.cc
@@ -307,9 +307,6 @@ BaseSimpleCPU::preExecute()
     SimpleExecContext &t_info = *threadInfo[curThread];
     SimpleThread* thread = t_info.thread;
 
-    // maintain $r0 semantics
-    thread->setIntReg(zeroReg, 0);
-
     // resets predicates
     t_info.setPredicate(true);
     t_info.setMemAccPredicate(true);
diff --git a/src/cpu/simple_thread.hh b/src/cpu/simple_thread.hh
index 73c75ff341..c2e620c202 100644
--- a/src/cpu/simple_thread.hh
+++ b/src/cpu/simple_thread.hh
@@ -405,6 +405,9 @@ class SimpleThread : public ThreadState, public ThreadContext
         auto &reg_file = regFiles[reg.classValue()];
         const auto &reg_class = reg_file.regClass;
 
+        if (reg.index() == reg_class.zeroReg())
+            return;
+
         DPRINTFV(reg_class.debug(), "Setting %s register %s (%d) to %#x.\n",
                 reg.className(), reg_class.regName(arch_reg), idx, val);
         reg_file.reg(idx) = val;
@@ -418,6 +421,9 @@ class SimpleThread : public ThreadState, public ThreadContext
         auto &reg_file = regFiles[reg.classValue()];
         const auto &reg_class = reg_file.regClass;
 
+        if (reg.index() == reg_class.zeroReg())
+            return;
+
         DPRINTFV(reg_class.debug(), "Setting %s register %d to %#x.\n",
                 reg.className(), idx, val);
         reg_file.reg(idx) = val;