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arch-x86: Respect LDT and TR bases in long mode.

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The LDT and TR bases *are* respected in 64 bit mode, so the base values
need to be set as specified.

Change-Id: Ieb1b58511d9651e6e59be199059b9d2b8c670472
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57049
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
This commit is contained in:
Gabe Black
2022-02-22 23:43:14 -08:00
parent 85b769a68e
commit 0e65df2cf5
1 changed files with 1 additions and 3 deletions
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4
src/arch/x86/fs_workload.cc
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@@ -66,9 +66,7 @@ installSegDesc(ThreadContext *tc, SegmentRegIndex seg,
SegDescriptor desc, bool longmode)
{
bool honorBase = !longmode || seg == SEGMENT_REG_FS ||
seg == SEGMENT_REG_GS ||
seg == SEGMENT_REG_TSL ||
seg == SYS_SEGMENT_REG_TR;
seg == SEGMENT_REG_GS;
SegAttr attr = 0;