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arch-x86: Fix some settings installed by the init interrupt.

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VMX requires that the present bit of the LDT and the TR are set, and
that the unusable bit of the TR is zero.

Change-Id: I4c4feba38d4fef11ad3b804d41dacb69cc3e6bd5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/57051
Maintainer: Gabe Black <gabe.black@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
This commit is contained in:
Gabe Black
2022-02-22 23:45:19 -08:00
parent 70ee16a387
commit 6cc3a27e09
1 changed files with 3 additions and 3 deletions
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6
src/arch/x86/faults.cc
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@@ -256,7 +256,7 @@ InitInterrupt::invoke(ThreadContext *tc, const StaticInstPtr &inst)
SegAttr tslAttr = 0;
tslAttr.unusable = 1;
tslAttr.present = 0;
tslAttr.present = 1;
tslAttr.type = 2; // LDT
tc->setMiscReg(MISCREG_TSL, 0);
tc->setMiscReg(MISCREG_TSL_BASE, 0);
@@ -264,8 +264,8 @@ InitInterrupt::invoke(ThreadContext *tc, const StaticInstPtr &inst)
tc->setMiscReg(MISCREG_TSL_ATTR, tslAttr);
SegAttr trAttr = 0;
trAttr.unusable = 1;
trAttr.present = 0;
trAttr.unusable = 0;
trAttr.present = 1;
trAttr.type = 3; // Busy 16-bit TSS
tc->setMiscReg(MISCREG_TR, 0);
tc->setMiscReg(MISCREG_TR_BASE, 0);