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arch-arm: Reuse MCR15 trapping code in DC instructions

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Change-Id: I08fec815400ad572da543660f0136e3d88d4dc65
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56593
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2021-12-21 12:15:02 +00:00
parent 31c31e1cd8
commit 0d65662218
1 changed files with 7 additions and 28 deletions
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35
src/arch/arm/isa/insts/misc.isa
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@@ -967,7 +967,7 @@ let {{
exec_output += PredOpExecute.subst(mrc15Iop)
mcr15code = '''
mcr15CheckCode = '''
int preFlatDest = snsBankedIndex(dest, xc->tcBase());
MiscRegIndex miscReg = (MiscRegIndex)
xc->tcBase()->flattenRegId(RegId(MiscRegClass,
@@ -989,6 +989,8 @@ let {{
if (fault != NoFault) {
return fault;
}
'''
mcr15code = mcr15CheckCode + '''
MiscNsBankedDest = Op1;
'''
mcr15Iop = ArmInstObjParams("mcr", "Mcr15", "MiscRegRegImmOp",
@@ -1110,29 +1112,6 @@ let {{
decoder_output += BasicConstructor.subst(clrexIop)
exec_output += PredOpExecute.subst(clrexIop)
McrDcCheckCode = '''
int preFlatDest = snsBankedIndex(dest, xc->tcBase());
MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
RegId(MiscRegClass, preFlatDest)).index();
Fault fault = mcrMrc15Trap(miscReg, machInst, xc->tcBase(), imm);
auto [can_write, undefined] = canWriteCoprocReg(miscReg, Scr, Cpsr,
xc->tcBase());
// if we're in non secure PL1 mode then we can trap regardless
// of whether the register is accessible, in other modes we
// trap if only if the register IS accessible.
if (undefined || (!can_write && !(fault != NoFault && !inUserMode(Cpsr) &&
!isSecure(xc->tcBase())))) {
return std::make_shared<UndefinedInstruction>(machInst, false,
mnemonic);
}
if (fault != NoFault) {
return fault;
}
'''
McrDcimvacCode = '''
const Request::Flags memAccessFlags(Request::INVALIDATE |
Request::DST_POC);
@@ -1140,7 +1119,7 @@ let {{
'''
McrDcimvacIop = ArmInstObjParams("mcr", "McrDcimvac",
"MiscRegRegImmOp",
{"memacc_code": McrDcCheckCode,
{"memacc_code": mcr15CheckCode,
"postacc_code": "",
"ea_code": McrDcimvacCode,
"predicate_test": predicateTest},
@@ -1158,7 +1137,7 @@ let {{
'''
McrDccmvacIop = ArmInstObjParams("mcr", "McrDccmvac",
"MiscRegRegImmOp",
{"memacc_code": McrDcCheckCode,
{"memacc_code": mcr15CheckCode,
"postacc_code": "",
"ea_code": McrDccmvacCode,
"predicate_test": predicateTest},
@@ -1176,7 +1155,7 @@ let {{
'''
McrDccmvauIop = ArmInstObjParams("mcr", "McrDccmvau",
"MiscRegRegImmOp",
{"memacc_code": McrDcCheckCode,
{"memacc_code": mcr15CheckCode,
"postacc_code": "",
"ea_code": McrDccmvauCode,
"predicate_test": predicateTest},
@@ -1195,7 +1174,7 @@ let {{
'''
McrDccimvacIop = ArmInstObjParams("mcr", "McrDccimvac",
"MiscRegRegImmOp",
{"memacc_code": McrDcCheckCode,
{"memacc_code": mcr15CheckCode,
"postacc_code": "",
"ea_code": McrDccimvacCode,
"predicate_test": predicateTest},