From 0d6566221899daa6f07e429b1673842a6ac00cd1 Mon Sep 17 00:00:00 2001
From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Tue, 21 Dec 2021 12:15:02 +0000
Subject: [PATCH] arch-arm: Reuse MCR15 trapping code in DC instructions

Change-Id: I08fec815400ad572da543660f0136e3d88d4dc65
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/56593
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
---
 src/arch/arm/isa/insts/misc.isa | 35 +++++++--------------------------
 1 file changed, 7 insertions(+), 28 deletions(-)

diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index c5ab3fa20d..72c8d68c45 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -967,7 +967,7 @@ let {{
     exec_output += PredOpExecute.subst(mrc15Iop)
 
 
-    mcr15code = '''
+    mcr15CheckCode = '''
     int preFlatDest = snsBankedIndex(dest, xc->tcBase());
     MiscRegIndex miscReg = (MiscRegIndex)
                        xc->tcBase()->flattenRegId(RegId(MiscRegClass,
@@ -989,6 +989,8 @@ let {{
     if (fault != NoFault) {
         return fault;
     }
+    '''
+    mcr15code = mcr15CheckCode + '''
     MiscNsBankedDest = Op1;
     '''
     mcr15Iop = ArmInstObjParams("mcr", "Mcr15", "MiscRegRegImmOp",
@@ -1110,29 +1112,6 @@ let {{
     decoder_output += BasicConstructor.subst(clrexIop)
     exec_output += PredOpExecute.subst(clrexIop)
 
-    McrDcCheckCode = '''
-        int preFlatDest = snsBankedIndex(dest, xc->tcBase());
-        MiscRegIndex miscReg = (MiscRegIndex) xc->tcBase()->flattenRegId(
-            RegId(MiscRegClass, preFlatDest)).index();
-
-        Fault fault = mcrMrc15Trap(miscReg, machInst, xc->tcBase(), imm);
-
-        auto [can_write, undefined] = canWriteCoprocReg(miscReg, Scr, Cpsr,
-                                                        xc->tcBase());
-
-        // if we're in non secure PL1 mode then we can trap regardless
-        // of whether the register is accessible, in other modes we
-        // trap if only if the register IS accessible.
-        if (undefined || (!can_write && !(fault != NoFault && !inUserMode(Cpsr) &&
-                                         !isSecure(xc->tcBase())))) {
-            return std::make_shared<UndefinedInstruction>(machInst, false,
-                                                          mnemonic);
-        }
-        if (fault != NoFault) {
-            return fault;
-        }
-    '''
-
     McrDcimvacCode = '''
         const Request::Flags memAccessFlags(Request::INVALIDATE |
                                             Request::DST_POC);
@@ -1140,7 +1119,7 @@ let {{
     '''
     McrDcimvacIop = ArmInstObjParams("mcr", "McrDcimvac",
                                      "MiscRegRegImmOp",
-                                     {"memacc_code": McrDcCheckCode,
+                                     {"memacc_code": mcr15CheckCode,
                                       "postacc_code": "",
                                       "ea_code": McrDcimvacCode,
                                       "predicate_test": predicateTest},
@@ -1158,7 +1137,7 @@ let {{
     '''
     McrDccmvacIop = ArmInstObjParams("mcr", "McrDccmvac",
                                      "MiscRegRegImmOp",
-                                     {"memacc_code": McrDcCheckCode,
+                                     {"memacc_code": mcr15CheckCode,
                                       "postacc_code": "",
                                       "ea_code": McrDccmvacCode,
                                       "predicate_test": predicateTest},
@@ -1176,7 +1155,7 @@ let {{
     '''
     McrDccmvauIop = ArmInstObjParams("mcr", "McrDccmvau",
                                      "MiscRegRegImmOp",
-                                     {"memacc_code": McrDcCheckCode,
+                                     {"memacc_code": mcr15CheckCode,
                                       "postacc_code": "",
                                       "ea_code": McrDccmvauCode,
                                       "predicate_test": predicateTest},
@@ -1195,7 +1174,7 @@ let {{
     '''
     McrDccimvacIop = ArmInstObjParams("mcr", "McrDccimvac",
                                      "MiscRegRegImmOp",
-                                     {"memacc_code": McrDcCheckCode,
+                                     {"memacc_code": mcr15CheckCode,
                                       "postacc_code": "",
                                       "ea_code": McrDccimvacCode,
                                       "predicate_test": predicateTest},