arch-arm: Use the new OperandDesc classes in the ISA description.
Change-Id: Ifacfdfb69014becae66f7497230cc8333950ddd9 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49728 Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com> Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com> Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
@@ -126,215 +126,236 @@ let {{
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srtMode = 1
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srtEPC = 0
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def vectorElem(idx):
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flat_idx = f'((({idx}) / 4) * NumVecElemPerVecReg) + ({idx}) % 4'
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return ('VecElem', 'sf', flat_idx, 'IsVectorElem', srtNormal)
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class VectorElem(VecElemOp):
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def __init__(self, idx):
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flat_idx = f'((({idx}) / 4) * NumVecElemPerVecReg) + ({idx}) % 4'
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super().__init__('sf', flat_idx, 'IsVectorElem', srtNormal)
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def vectorReg(idx, base, suffix = ''):
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elems = {
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base + 'P0' + suffix : ('0', 'sf'),
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base + 'P1' + suffix : ('1', 'sf'),
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base + 'P2' + suffix : ('2', 'sf'),
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base + 'P3' + suffix : ('3', 'sf'),
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base + 'S' + suffix : ('0', 'sf'),
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base + 'D' + suffix : ('0', 'df'),
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base + 'Q' + suffix : ('0', 'tud')
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}
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return ('VecReg', 'vc', (idx, elems), 'IsVector', srtNormal)
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class VectorReg(VecRegOp):
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def __init__(self, idx, base, suffix=''):
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elems = {
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base + 'P0' + suffix : ('0', 'sf'),
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base + 'P1' + suffix : ('1', 'sf'),
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base + 'P2' + suffix : ('2', 'sf'),
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base + 'P3' + suffix : ('3', 'sf'),
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base + 'S' + suffix : ('0', 'sf'),
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base + 'D' + suffix : ('0', 'df'),
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base + 'Q' + suffix : ('0', 'tud')
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}
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super().__init__('vc', (idx, elems), 'IsVector', srtNormal)
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def vecPredReg(idx):
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return ('VecPredReg', 'pc', idx, None, srtNormal)
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class VecPredReg(VecPredRegOp):
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def __init__(self, idx):
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super().__init__('pc', idx, sort_pri=srtNormal)
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def intReg(idx):
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return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
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maybePCRead, maybePCWrite)
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class IntReg(IntRegOp):
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read_code = maybePCRead
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write_code = maybePCWrite
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def __init__(self, idx, ctype='uw', id=srtNormal):
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super().__init__(ctype, idx, 'IsInteger', id,
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read_code=self.read_code, write_code=self.write_code)
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def pIntReg(idx):
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return ('IntReg', 'pint', idx, 'IsInteger', srtNormal,
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maybePCRead, maybePCWrite)
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class PIntReg(IntReg):
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def __init__(self, idx):
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super().__init__(idx, ctype='pint')
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def intReg64(idx):
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return ('IntReg', 'ud', idx, 'IsInteger', srtNormal,
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aarch64Read, aarch64Write)
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class IntRegNPC(IntReg):
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read_code = None
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write_code = None
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def intRegX64(idx, id = srtNormal):
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return ('IntReg', 'ud', idx, 'IsInteger', id,
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aarchX64Read, aarchX64Write)
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class IntRegAPC(IntReg):
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read_code = maybeAlignedPCRead
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def intRegW64(idx, id = srtNormal):
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return ('IntReg', 'ud', idx, 'IsInteger', id,
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aarchW64Read, aarchW64Write)
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class IntRegIWPC(IntReg):
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write_code = maybeIWPCWrite
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def intRegNPC(idx):
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return ('IntReg', 'uw', idx, 'IsInteger', srtNormal)
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class IntRegAIWPC(IntReg):
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write_code = maybeAIWPCWrite
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def intRegAPC(idx, id = srtNormal):
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return ('IntReg', 'uw', idx, 'IsInteger', id,
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maybeAlignedPCRead, maybePCWrite)
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class IntReg64(IntRegOp):
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read_code = aarch64Read
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write_code = aarch64Write
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def __init__(self, idx, id=srtNormal):
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super().__init__('ud', idx, 'IsInteger', id,
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read_code=self.read_code, write_code=self.write_code)
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def intRegIWPC(idx):
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return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
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maybePCRead, maybeIWPCWrite)
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class IntRegX64(IntReg64):
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read_code = aarchX64Read
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write_code = aarchX64Write
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def intRegAIWPC(idx):
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return ('IntReg', 'uw', idx, 'IsInteger', srtNormal,
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maybePCRead, maybeAIWPCWrite)
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class IntRegW64(IntReg64):
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read_code = aarchW64Read
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write_code = aarchW64Write
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def ccReg(idx):
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return ('CCReg', 'uw', idx, None, srtNormal)
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class CCReg(CCRegOp):
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def __init__(self, idx):
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super().__init__('uw', idx, sort_pri=srtNormal)
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def cntrlReg(idx, id = srtNormal, type = 'uw'):
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return ('ControlReg', type, idx, None, id)
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class CntrlReg(ControlRegOp):
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read_code = None
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write_code = None
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flags = None
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def __init__(self, idx, id=srtNormal, ctype='uw'):
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super().__init__(ctype, idx, sort_pri=id,
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read_code=self.read_code, write_code=self.write_code,
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flags=self.flags)
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def cntrlNsBankedReg(idx, id = srtNormal, type = 'uw'):
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return ('ControlReg', type, idx, (None, None, 'IsControl'), id, cntrlNsBankedRead, cntrlNsBankedWrite)
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class CntrlNsBankedReg(CntrlReg):
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read_code = cntrlNsBankedRead
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write_code = cntrlNsBankedWrite
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flags = (None, None, 'IsControl')
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def __init__(self, idx, id=srtNormal, ctype='uw'):
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super().__init__(idx, id, ctype)
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def cntrlNsBankedReg64(idx, id = srtNormal, type = 'ud'):
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return ('ControlReg', type, idx, (None, None, 'IsControl'), id, cntrlNsBankedRead, cntrlNsBankedWrite)
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class CntrlNsBankedReg64(CntrlNsBankedReg):
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def __init__(self, idx, id=srtNormal, ctype='ud'):
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super().__init__(idx, id, ctype)
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def cntrlRegNC(idx, id = srtNormal, type = 'uw'):
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return ('ControlReg', type, idx, None, id)
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class CntrlRegNC(CntrlReg):
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pass
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def pcStateReg(idx, id):
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return ('PCState', 'ud', idx, (None, None, 'IsControl'), id)
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class PCStateReg(PCStateOp):
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def __init__(self, idx, id):
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super().__init__('ud', idx, (None, None, 'IsControl'), id)
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}};
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def operands {{
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#Abstracted integer reg operands
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'Dest': intReg('dest'),
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'Dest64': intReg64('dest'),
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'XDest': intRegX64('dest'),
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'WDest': intRegW64('dest'),
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'IWDest': intRegIWPC('dest'),
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'AIWDest': intRegAIWPC('dest'),
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'Dest2': intReg('dest2'),
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'XDest2': intRegX64('dest2'),
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'IWDest2': intRegIWPC('dest2'),
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'Result': intReg('result'),
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'XResult': intRegX64('result'),
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'XResult2': intRegX64('result2'),
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'XBase': intRegX64('base', id = srtBase),
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'Base': intRegAPC('base', id = srtBase),
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'XOffset': intRegX64('offset'),
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'Index': intReg('index'),
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'Shift': intReg('shift'),
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'Op1': intReg('op1'),
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'Op2': intReg('op2'),
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'Op3': intReg('op3'),
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'Op164': intReg64('op1'),
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'Op264': intReg64('op2'),
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'Op364': intReg64('op3'),
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'XOp1': intRegX64('op1'),
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'XOp2': intRegX64('op2'),
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'XOp3': intRegX64('op3'),
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'WOp1': intRegW64('op1'),
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'WOp2': intRegW64('op2'),
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'WOp3': intRegW64('op3'),
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'Reg0': intReg('reg0'),
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'Reg1': intReg('reg1'),
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'Reg2': intReg('reg2'),
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'Reg3': intReg('reg3'),
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'PInt0': pIntReg('reg0'),
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'PInt1': pIntReg('reg1'),
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'PInt2': pIntReg('reg2'),
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'PInt3': pIntReg('reg3'),
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'Dest': IntReg('dest'),
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'Dest64': IntReg64('dest'),
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'XDest': IntRegX64('dest'),
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'WDest': IntRegW64('dest'),
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'IWDest': IntRegIWPC('dest'),
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'AIWDest': IntRegAIWPC('dest'),
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'Dest2': IntReg('dest2'),
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'XDest2': IntRegX64('dest2'),
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'IWDest2': IntRegIWPC('dest2'),
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'Result': IntReg('result'),
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'XResult': IntRegX64('result'),
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'XResult2': IntRegX64('result2'),
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'XBase': IntRegX64('base', id=srtBase),
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'Base': IntRegAPC('base', id=srtBase),
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'XOffset': IntRegX64('offset'),
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'Index': IntReg('index'),
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'Shift': IntReg('shift'),
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'Op1': IntReg('op1'),
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'Op2': IntReg('op2'),
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'Op3': IntReg('op3'),
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'Op164': IntReg64('op1'),
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'Op264': IntReg64('op2'),
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'Op364': IntReg64('op3'),
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'XOp1': IntRegX64('op1'),
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'XOp2': IntRegX64('op2'),
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'XOp3': IntRegX64('op3'),
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'WOp1': IntRegW64('op1'),
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'WOp2': IntRegW64('op2'),
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'WOp3': IntRegW64('op3'),
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'Reg0': IntReg('reg0'),
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'Reg1': IntReg('reg1'),
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'Reg2': IntReg('reg2'),
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'Reg3': IntReg('reg3'),
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'PInt0': PIntReg('reg0'),
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'PInt1': PIntReg('reg1'),
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'PInt2': PIntReg('reg2'),
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'PInt3': PIntReg('reg3'),
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#Fixed index integer reg operands
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'SpMode': intRegNPC('intRegInMode((OperatingMode)regMode, INTREG_SP)'),
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'DecodedBankedIntReg': intRegNPC('decodeMrsMsrBankedIntRegIndex(byteMask, r)'),
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'LR': intRegNPC('INTREG_LR'),
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'XLR': intRegX64('INTREG_X30'),
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'R7': intRegNPC('7'),
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'SpMode': IntRegNPC('intRegInMode((OperatingMode)regMode, INTREG_SP)'),
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'DecodedBankedIntReg':
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IntRegNPC('decodeMrsMsrBankedIntRegIndex(byteMask, r)'),
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'LR': IntRegNPC('INTREG_LR'),
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'XLR': IntRegX64('INTREG_X30'),
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'R7': IntRegNPC('7'),
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# First four arguments are passed in registers
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'R0': intRegNPC('0'),
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'R1': intRegNPC('1'),
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'R2': intRegNPC('2'),
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'R3': intRegNPC('3'),
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'R4': intRegNPC('4'),
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'R5': intRegNPC('5'),
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'X0': intRegX64('0'),
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'X1': intRegX64('1'),
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'X2': intRegX64('2'),
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'X3': intRegX64('3'),
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'X4': intRegX64('4'),
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'X5': intRegX64('5'),
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'R0': IntRegNPC('0'),
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'R1': IntRegNPC('1'),
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'R2': IntRegNPC('2'),
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'R3': IntRegNPC('3'),
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'R4': IntRegNPC('4'),
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'R5': IntRegNPC('5'),
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'X0': IntRegX64('0'),
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'X1': IntRegX64('1'),
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'X2': IntRegX64('2'),
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'X3': IntRegX64('3'),
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'X4': IntRegX64('4'),
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'X5': IntRegX64('5'),
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# Condition code registers
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'CondCodesNZ': ccReg('CCREG_NZ'),
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'CondCodesC': ccReg('CCREG_C'),
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'CondCodesV': ccReg('CCREG_V'),
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'CondCodesGE': ccReg('CCREG_GE'),
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'OptCondCodesNZ': ccReg(
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'CondCodesNZ': CCReg('CCREG_NZ'),
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'CondCodesC': CCReg('CCREG_C'),
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'CondCodesV': CCReg('CCREG_V'),
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'CondCodesGE': CCReg('CCREG_GE'),
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'OptCondCodesNZ': CCReg(
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'''((condCode == COND_AL || condCode == COND_UC ||
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condCode == COND_CC || condCode == COND_CS ||
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condCode == COND_VS || condCode == COND_VC) ?
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CCREG_ZERO : CCREG_NZ)'''),
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'OptCondCodesC': ccReg(
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'OptCondCodesC': CCReg(
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'''((condCode == COND_HI || condCode == COND_LS ||
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condCode == COND_CS || condCode == COND_CC) ?
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CCREG_C : CCREG_ZERO)'''),
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'OptShiftRmCondCodesC': ccReg(
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'OptShiftRmCondCodesC': CCReg(
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'''((condCode == COND_HI || condCode == COND_LS ||
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condCode == COND_CS || condCode == COND_CC ||
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shiftType == ROR) ?
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CCREG_C : CCREG_ZERO)'''),
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'OptCondCodesV': ccReg(
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'OptCondCodesV': CCReg(
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'''((condCode == COND_VS || condCode == COND_VC ||
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condCode == COND_GE || condCode == COND_LT ||
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condCode == COND_GT || condCode == COND_LE) ?
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CCREG_V : CCREG_ZERO)'''),
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'FpCondCodes': ccReg('CCREG_FP'),
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'FpCondCodes': CCReg('CCREG_FP'),
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#Abstracted floating point reg operands
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'FpDest': vectorElem('dest'),
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'FpDestP0': vectorElem('dest + 0'),
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'FpDestP1': vectorElem('dest + 1'),
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'FpDestP2': vectorElem('dest + 2'),
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'FpDestP3': vectorElem('dest + 3'),
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'FpDestP4': vectorElem('dest + 4'),
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'FpDestP5': vectorElem('dest + 5'),
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'FpDestP6': vectorElem('dest + 6'),
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'FpDestP7': vectorElem('dest + 7'),
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'FpDest': VectorElem('dest'),
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'FpDestP0': VectorElem('dest + 0'),
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'FpDestP1': VectorElem('dest + 1'),
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'FpDestP2': VectorElem('dest + 2'),
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'FpDestP3': VectorElem('dest + 3'),
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'FpDestP4': VectorElem('dest + 4'),
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'FpDestP5': VectorElem('dest + 5'),
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'FpDestP6': VectorElem('dest + 6'),
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'FpDestP7': VectorElem('dest + 7'),
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'FpDestS0P0': vectorElem('dest + step * 0 + 0'),
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'FpDestS0P1': vectorElem('dest + step * 0 + 1'),
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'FpDestS1P0': vectorElem('dest + step * 1 + 0'),
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'FpDestS1P1': vectorElem('dest + step * 1 + 1'),
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'FpDestS2P0': vectorElem('dest + step * 2 + 0'),
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'FpDestS2P1': vectorElem('dest + step * 2 + 1'),
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'FpDestS3P0': vectorElem('dest + step * 3 + 0'),
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'FpDestS3P1': vectorElem('dest + step * 3 + 1'),
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'FpDestS0P0': VectorElem('dest + step * 0 + 0'),
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'FpDestS0P1': VectorElem('dest + step * 0 + 1'),
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'FpDestS1P0': VectorElem('dest + step * 1 + 0'),
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'FpDestS1P1': VectorElem('dest + step * 1 + 1'),
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'FpDestS2P0': VectorElem('dest + step * 2 + 0'),
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'FpDestS2P1': VectorElem('dest + step * 2 + 1'),
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'FpDestS3P0': VectorElem('dest + step * 3 + 0'),
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'FpDestS3P1': VectorElem('dest + step * 3 + 1'),
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'FpDest2': vectorElem('dest2'),
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'FpDest2P0': vectorElem('dest2 + 0'),
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'FpDest2P1': vectorElem('dest2 + 1'),
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'FpDest2P2': vectorElem('dest2 + 2'),
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'FpDest2P3': vectorElem('dest2 + 3'),
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'FpDest2': VectorElem('dest2'),
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'FpDest2P0': VectorElem('dest2 + 0'),
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'FpDest2P1': VectorElem('dest2 + 1'),
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'FpDest2P2': VectorElem('dest2 + 2'),
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'FpDest2P3': VectorElem('dest2 + 3'),
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'FpOp1': vectorElem('op1'),
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'FpOp1P0': vectorElem('op1 + 0'),
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'FpOp1P1': vectorElem('op1 + 1'),
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'FpOp1P2': vectorElem('op1 + 2'),
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'FpOp1P3': vectorElem('op1 + 3'),
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'FpOp1P4': vectorElem('op1 + 4'),
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'FpOp1P5': vectorElem('op1 + 5'),
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'FpOp1P6': vectorElem('op1 + 6'),
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'FpOp1P7': vectorElem('op1 + 7'),
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'FpOp1': VectorElem('op1'),
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'FpOp1P0': VectorElem('op1 + 0'),
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'FpOp1P1': VectorElem('op1 + 1'),
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'FpOp1P2': VectorElem('op1 + 2'),
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'FpOp1P3': VectorElem('op1 + 3'),
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'FpOp1P4': VectorElem('op1 + 4'),
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'FpOp1P5': VectorElem('op1 + 5'),
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'FpOp1P6': VectorElem('op1 + 6'),
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'FpOp1P7': VectorElem('op1 + 7'),
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'FpOp1S0P0': vectorElem('op1 + step * 0 + 0'),
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'FpOp1S0P1': vectorElem('op1 + step * 0 + 1'),
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'FpOp1S1P0': vectorElem('op1 + step * 1 + 0'),
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'FpOp1S1P1': vectorElem('op1 + step * 1 + 1'),
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'FpOp1S2P0': vectorElem('op1 + step * 2 + 0'),
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'FpOp1S2P1': vectorElem('op1 + step * 2 + 1'),
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'FpOp1S3P0': vectorElem('op1 + step * 3 + 0'),
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'FpOp1S3P1': vectorElem('op1 + step * 3 + 1'),
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'FpOp1S0P0': VectorElem('op1 + step * 0 + 0'),
|
||||
'FpOp1S0P1': VectorElem('op1 + step * 0 + 1'),
|
||||
'FpOp1S1P0': VectorElem('op1 + step * 1 + 0'),
|
||||
'FpOp1S1P1': VectorElem('op1 + step * 1 + 1'),
|
||||
'FpOp1S2P0': VectorElem('op1 + step * 2 + 0'),
|
||||
'FpOp1S2P1': VectorElem('op1 + step * 2 + 1'),
|
||||
'FpOp1S3P0': VectorElem('op1 + step * 3 + 0'),
|
||||
'FpOp1S3P1': VectorElem('op1 + step * 3 + 1'),
|
||||
|
||||
'FpOp2': vectorElem('op2'),
|
||||
'FpOp2P0': vectorElem('op2 + 0'),
|
||||
'FpOp2P1': vectorElem('op2 + 1'),
|
||||
'FpOp2P2': vectorElem('op2 + 2'),
|
||||
'FpOp2P3': vectorElem('op2 + 3'),
|
||||
'FpOp2': VectorElem('op2'),
|
||||
'FpOp2P0': VectorElem('op2 + 0'),
|
||||
'FpOp2P1': VectorElem('op2 + 1'),
|
||||
'FpOp2P2': VectorElem('op2 + 2'),
|
||||
'FpOp2P3': VectorElem('op2 + 3'),
|
||||
|
||||
# Create AArch64 unpacked view of the FP registers
|
||||
# Name ::= 'AA64Vec' OpSpec [LaneSpec]
|
||||
@@ -348,112 +369,112 @@ def operands {{
|
||||
# All the constituents are hierarchically defined as part of the Vector
|
||||
# Register they belong to
|
||||
|
||||
'AA64FpOp1': vectorReg('op1', 'AA64FpOp1'),
|
||||
'AA64FpOp2': vectorReg('op2', 'AA64FpOp2'),
|
||||
'AA64FpOp3': vectorReg('op3', 'AA64FpOp3'),
|
||||
'AA64FpDest': vectorReg('dest', 'AA64FpDest'),
|
||||
'AA64FpDest2': vectorReg('dest2', 'AA64FpDest2'),
|
||||
'AA64FpOp1V0': vectorReg('op1', 'AA64FpOp1', 'V0'),
|
||||
'AA64FpOp1V1': vectorReg('op1 + 1', 'AA64FpOp1', 'V1'),
|
||||
'AA64FpOp1V2': vectorReg('op1 + 2', 'AA64FpOp1', 'V2'),
|
||||
'AA64FpOp1V3': vectorReg('op1 + 3', 'AA64FpOp1', 'V3'),
|
||||
'AA64FpOp1V0S': vectorReg('(op1 + 0) % 32', 'AA64FpOp1', 'V0S'),
|
||||
'AA64FpOp1V1S': vectorReg('(op1 + 1) % 32', 'AA64FpOp1', 'V1S'),
|
||||
'AA64FpOp1V2S': vectorReg('(op1 + 2) % 32', 'AA64FpOp1', 'V2S'),
|
||||
'AA64FpOp1V3S': vectorReg('(op1 + 3) % 32', 'AA64FpOp1', 'V3S'),
|
||||
'AA64FpDestV0': vectorReg('(dest + 0)', 'AA64FpDest', 'V0'),
|
||||
'AA64FpDestV1': vectorReg('(dest + 1)', 'AA64FpDest', 'V1'),
|
||||
'AA64FpDestV0L': vectorReg('(dest + 0) % 32', 'AA64FpDest', 'V0L'),
|
||||
'AA64FpDestV1L': vectorReg('(dest + 1) % 32', 'AA64FpDest', 'V1L'),
|
||||
'AA64FpOp1': VectorReg('op1', 'AA64FpOp1'),
|
||||
'AA64FpOp2': VectorReg('op2', 'AA64FpOp2'),
|
||||
'AA64FpOp3': VectorReg('op3', 'AA64FpOp3'),
|
||||
'AA64FpDest': VectorReg('dest', 'AA64FpDest'),
|
||||
'AA64FpDest2': VectorReg('dest2', 'AA64FpDest2'),
|
||||
'AA64FpOp1V0': VectorReg('op1', 'AA64FpOp1', 'V0'),
|
||||
'AA64FpOp1V1': VectorReg('op1 + 1', 'AA64FpOp1', 'V1'),
|
||||
'AA64FpOp1V2': VectorReg('op1 + 2', 'AA64FpOp1', 'V2'),
|
||||
'AA64FpOp1V3': VectorReg('op1 + 3', 'AA64FpOp1', 'V3'),
|
||||
'AA64FpOp1V0S': VectorReg('(op1 + 0) % 32', 'AA64FpOp1', 'V0S'),
|
||||
'AA64FpOp1V1S': VectorReg('(op1 + 1) % 32', 'AA64FpOp1', 'V1S'),
|
||||
'AA64FpOp1V2S': VectorReg('(op1 + 2) % 32', 'AA64FpOp1', 'V2S'),
|
||||
'AA64FpOp1V3S': VectorReg('(op1 + 3) % 32', 'AA64FpOp1', 'V3S'),
|
||||
'AA64FpDestV0': VectorReg('(dest + 0)', 'AA64FpDest', 'V0'),
|
||||
'AA64FpDestV1': VectorReg('(dest + 1)', 'AA64FpDest', 'V1'),
|
||||
'AA64FpDestV0L': VectorReg('(dest + 0) % 32', 'AA64FpDest', 'V0L'),
|
||||
'AA64FpDestV1L': VectorReg('(dest + 1) % 32', 'AA64FpDest', 'V1L'),
|
||||
|
||||
# Temporary registers for SVE interleaving
|
||||
'AA64IntrlvReg0': vectorReg('INTRLVREG0', 'AA64FpIntrlvReg0'),
|
||||
'AA64IntrlvReg1': vectorReg('INTRLVREG1', 'AA64FpIntrlvReg1'),
|
||||
'AA64IntrlvReg2': vectorReg('INTRLVREG2', 'AA64FpIntrlvReg2'),
|
||||
'AA64IntrlvReg3': vectorReg('INTRLVREG3', 'AA64FpIntrlvReg3'),
|
||||
'AA64FpDestMerge': vectorReg('dest', 'AA64FpDestMerge'),
|
||||
'AA64FpBase': vectorReg('base', 'AA64FpBase'),
|
||||
'AA64FpOffset': vectorReg('offset', 'AA64FpOffset'),
|
||||
'AA64FpUreg0': vectorReg('VECREG_UREG0', 'AA64FpUreg0'),
|
||||
'AA64IntrlvReg0': VectorReg('INTRLVREG0', 'AA64FpIntrlvReg0'),
|
||||
'AA64IntrlvReg1': VectorReg('INTRLVREG1', 'AA64FpIntrlvReg1'),
|
||||
'AA64IntrlvReg2': VectorReg('INTRLVREG2', 'AA64FpIntrlvReg2'),
|
||||
'AA64IntrlvReg3': VectorReg('INTRLVREG3', 'AA64FpIntrlvReg3'),
|
||||
'AA64FpDestMerge': VectorReg('dest', 'AA64FpDestMerge'),
|
||||
'AA64FpBase': VectorReg('base', 'AA64FpBase'),
|
||||
'AA64FpOffset': VectorReg('offset', 'AA64FpOffset'),
|
||||
'AA64FpUreg0': VectorReg('VECREG_UREG0', 'AA64FpUreg0'),
|
||||
|
||||
# Predicate register operands
|
||||
'GpOp': vecPredReg('gp'),
|
||||
'POp1': vecPredReg('op1'),
|
||||
'POp2': vecPredReg('op2'),
|
||||
'PDest': vecPredReg('dest'),
|
||||
'PDestMerge': vecPredReg('dest'),
|
||||
'Ffr': vecPredReg('PREDREG_FFR'),
|
||||
'FfrAux': vecPredReg('PREDREG_FFR'),
|
||||
'PUreg0': vecPredReg('PREDREG_UREG0'),
|
||||
'GpOp': VecPredReg('gp'),
|
||||
'POp1': VecPredReg('op1'),
|
||||
'POp2': VecPredReg('op2'),
|
||||
'PDest': VecPredReg('dest'),
|
||||
'PDestMerge': VecPredReg('dest'),
|
||||
'Ffr': VecPredReg('PREDREG_FFR'),
|
||||
'FfrAux': VecPredReg('PREDREG_FFR'),
|
||||
'PUreg0': VecPredReg('PREDREG_UREG0'),
|
||||
|
||||
#Abstracted control reg operands
|
||||
'MiscDest': cntrlReg('dest'),
|
||||
'MiscOp1': cntrlReg('op1'),
|
||||
'MiscNsBankedDest': cntrlNsBankedReg('dest'),
|
||||
'MiscNsBankedOp1': cntrlNsBankedReg('op1'),
|
||||
'MiscNsBankedDest64': cntrlNsBankedReg64('dest'),
|
||||
'MiscNsBankedOp164': cntrlNsBankedReg64('op1'),
|
||||
'MiscDest': CntrlReg('dest'),
|
||||
'MiscOp1': CntrlReg('op1'),
|
||||
'MiscNsBankedDest': CntrlNsBankedReg('dest'),
|
||||
'MiscNsBankedOp1': CntrlNsBankedReg('op1'),
|
||||
'MiscNsBankedDest64': CntrlNsBankedReg64('dest'),
|
||||
'MiscNsBankedOp164': CntrlNsBankedReg64('op1'),
|
||||
|
||||
#Fixed index control regs
|
||||
'Cpsr': cntrlReg('MISCREG_CPSR', srtCpsr),
|
||||
'CpsrQ': cntrlReg('MISCREG_CPSR_Q', srtCpsr),
|
||||
'Spsr': cntrlRegNC('MISCREG_SPSR'),
|
||||
'Fpsr': cntrlRegNC('MISCREG_FPSR'),
|
||||
'Fpsid': cntrlRegNC('MISCREG_FPSID'),
|
||||
'Fpscr': cntrlRegNC('MISCREG_FPSCR'),
|
||||
'FpscrQc': cntrlRegNC('MISCREG_FPSCR_QC'),
|
||||
'FpscrExc': cntrlRegNC('MISCREG_FPSCR_EXC'),
|
||||
'Cpacr': cntrlReg('MISCREG_CPACR'),
|
||||
'Cpacr64': cntrlReg('MISCREG_CPACR_EL1'),
|
||||
'Fpexc': cntrlRegNC('MISCREG_FPEXC'),
|
||||
'Nsacr': cntrlReg('MISCREG_NSACR'),
|
||||
'ElrHyp': cntrlRegNC('MISCREG_ELR_HYP'),
|
||||
'Hcr': cntrlReg('MISCREG_HCR'),
|
||||
'Hcr64': cntrlReg('MISCREG_HCR_EL2'),
|
||||
'CptrEl264': cntrlReg('MISCREG_CPTR_EL2'),
|
||||
'CptrEl364': cntrlReg('MISCREG_CPTR_EL3'),
|
||||
'Hstr': cntrlReg('MISCREG_HSTR'),
|
||||
'Scr': cntrlReg('MISCREG_SCR'),
|
||||
'Scr64': cntrlReg('MISCREG_SCR_EL3'),
|
||||
'Sctlr': cntrlRegNC('MISCREG_SCTLR'),
|
||||
'SevMailbox': cntrlRegNC('MISCREG_SEV_MAILBOX'),
|
||||
'LLSCLock': cntrlRegNC('MISCREG_LOCKFLAG'),
|
||||
'Dczid' : cntrlRegNC('MISCREG_DCZID_EL0'),
|
||||
'PendingDvm': cntrlRegNC('MISCREG_TLBINEEDSYNC'),
|
||||
'Cpsr': CntrlReg('MISCREG_CPSR', srtCpsr),
|
||||
'CpsrQ': CntrlReg('MISCREG_CPSR_Q', srtCpsr),
|
||||
'Spsr': CntrlRegNC('MISCREG_SPSR'),
|
||||
'Fpsr': CntrlRegNC('MISCREG_FPSR'),
|
||||
'Fpsid': CntrlRegNC('MISCREG_FPSID'),
|
||||
'Fpscr': CntrlRegNC('MISCREG_FPSCR'),
|
||||
'FpscrQc': CntrlRegNC('MISCREG_FPSCR_QC'),
|
||||
'FpscrExc': CntrlRegNC('MISCREG_FPSCR_EXC'),
|
||||
'Cpacr': CntrlReg('MISCREG_CPACR'),
|
||||
'Cpacr64': CntrlReg('MISCREG_CPACR_EL1'),
|
||||
'Fpexc': CntrlRegNC('MISCREG_FPEXC'),
|
||||
'Nsacr': CntrlReg('MISCREG_NSACR'),
|
||||
'ElrHyp': CntrlRegNC('MISCREG_ELR_HYP'),
|
||||
'Hcr': CntrlReg('MISCREG_HCR'),
|
||||
'Hcr64': CntrlReg('MISCREG_HCR_EL2'),
|
||||
'CptrEl264': CntrlReg('MISCREG_CPTR_EL2'),
|
||||
'CptrEl364': CntrlReg('MISCREG_CPTR_EL3'),
|
||||
'Hstr': CntrlReg('MISCREG_HSTR'),
|
||||
'Scr': CntrlReg('MISCREG_SCR'),
|
||||
'Scr64': CntrlReg('MISCREG_SCR_EL3'),
|
||||
'Sctlr': CntrlRegNC('MISCREG_SCTLR'),
|
||||
'SevMailbox': CntrlRegNC('MISCREG_SEV_MAILBOX'),
|
||||
'LLSCLock': CntrlRegNC('MISCREG_LOCKFLAG'),
|
||||
'Dczid' : CntrlRegNC('MISCREG_DCZID_EL0'),
|
||||
'PendingDvm': CntrlRegNC('MISCREG_TLBINEEDSYNC'),
|
||||
|
||||
#Register fields for microops
|
||||
'URa' : intReg('ura'),
|
||||
'XURa' : intRegX64('ura'),
|
||||
'WURa' : intRegW64('ura'),
|
||||
'IWRa' : intRegIWPC('ura'),
|
||||
'Fa' : vectorElem('ura'),
|
||||
'URb' : intReg('urb'),
|
||||
'XURb' : intRegX64('urb'),
|
||||
'URc' : intReg('urc'),
|
||||
'XURc' : intRegX64('urc'),
|
||||
'URa' : IntReg('ura'),
|
||||
'XURa' : IntRegX64('ura'),
|
||||
'WURa' : IntRegW64('ura'),
|
||||
'IWRa' : IntRegIWPC('ura'),
|
||||
'Fa' : VectorElem('ura'),
|
||||
'URb' : IntReg('urb'),
|
||||
'XURb' : IntRegX64('urb'),
|
||||
'URc' : IntReg('urc'),
|
||||
'XURc' : IntRegX64('urc'),
|
||||
|
||||
#Memory Operand
|
||||
'Mem': ('Mem', 'uw', None, (None, 'IsLoad', 'IsStore'), srtNormal),
|
||||
'Mem': MemOp('uw', None, (None, 'IsLoad', 'IsStore'), srtNormal),
|
||||
|
||||
#PCState fields
|
||||
'RawPC': pcStateReg('pc', srtPC),
|
||||
'PC': pcStateReg('instPC', srtPC),
|
||||
'NPC': pcStateReg('instNPC', srtPC),
|
||||
'pNPC': pcStateReg('instNPC', srtEPC),
|
||||
'IWNPC': pcStateReg('instIWNPC', srtPC),
|
||||
'Thumb': pcStateReg('thumb', srtPC),
|
||||
'NextThumb': pcStateReg('nextThumb', srtMode),
|
||||
'NextJazelle': pcStateReg('nextJazelle', srtMode),
|
||||
'NextItState': pcStateReg('nextItstate', srtMode),
|
||||
'Itstate': pcStateReg('itstate', srtMode),
|
||||
'NextAArch64': pcStateReg('nextAArch64', srtMode),
|
||||
'RawPC': PCStateReg('pc', srtPC),
|
||||
'PC': PCStateReg('instPC', srtPC),
|
||||
'NPC': PCStateReg('instNPC', srtPC),
|
||||
'pNPC': PCStateReg('instNPC', srtEPC),
|
||||
'IWNPC': PCStateReg('instIWNPC', srtPC),
|
||||
'Thumb': PCStateReg('thumb', srtPC),
|
||||
'NextThumb': PCStateReg('nextThumb', srtMode),
|
||||
'NextJazelle': PCStateReg('nextJazelle', srtMode),
|
||||
'NextItState': PCStateReg('nextItstate', srtMode),
|
||||
'Itstate': PCStateReg('itstate', srtMode),
|
||||
'NextAArch64': PCStateReg('nextAArch64', srtMode),
|
||||
|
||||
#Register operands depending on a field in the instruction encoding. These
|
||||
#should be avoided since they may not be portable across different
|
||||
#encodings of the same instruction.
|
||||
'Rd': intReg('RD'),
|
||||
'Rm': intReg('RM'),
|
||||
'Rs': intReg('RS'),
|
||||
'Rn': intReg('RN'),
|
||||
'Rt': intReg('RT')
|
||||
'Rd': IntReg('RD'),
|
||||
'Rm': IntReg('RM'),
|
||||
'Rs': IntReg('RS'),
|
||||
'Rn': IntReg('RN'),
|
||||
'Rt': IntReg('RT')
|
||||
}};
|
||||
|
||||
Reference in New Issue
Block a user