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arm: Use custom RegClassOps for vector and vector pred registers.

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Change-Id: Icef429d5c9c036541472c470d5009c8d29a74548
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49695
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Gabe Black
2021-08-11 03:25:02 -07:00
parent 6cc3a27e09
commit 322f1d8fe7
1 changed files with 6 additions and 2 deletions
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8
src/arch/arm/isa.cc
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@@ -81,6 +81,8 @@ class MiscRegClassOps : public RegClassOps
} miscRegClassOps;
VecElemRegClassOps<ArmISA::VecElem> vecRegElemClassOps(NumVecElemPerVecReg);
TypedRegClassOps<ArmISA::VecRegContainer> vecRegClassOps;
TypedRegClassOps<ArmISA::VecPredRegContainer> vecPredRegClassOps;
ISA::ISA(const Params &p) : BaseISA(p), system(NULL),
_decoderFlavor(p.decoderFlavor), pmu(p.pmu), impdefAsNop(p.impdef_nop),
@@ -88,10 +90,12 @@ ISA::ISA(const Params &p) : BaseISA(p), system(NULL),
{
_regClasses.emplace_back(NUM_INTREGS, INTREG_ZERO);
_regClasses.emplace_back(0);
_regClasses.emplace_back(NumVecRegs, -1, sizeof(VecRegContainer));
_regClasses.emplace_back(NumVecRegs, vecRegClassOps, -1,
sizeof(VecRegContainer));
_regClasses.emplace_back(NumVecRegs * NumVecElemPerVecReg,
vecRegElemClassOps);
_regClasses.emplace_back(NumVecPredRegs, -1, sizeof(VecPredRegContainer));
_regClasses.emplace_back(NumVecPredRegs, vecPredRegClassOps, -1,
sizeof(VecPredRegContainer));
_regClasses.emplace_back(NUM_CCREGS);
_regClasses.emplace_back(NUM_MISCREGS, miscRegClassOps);