diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index ed4cf24d83..0db133b0f0 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -81,6 +81,8 @@ class MiscRegClassOps : public RegClassOps
 } miscRegClassOps;
 
 VecElemRegClassOps<ArmISA::VecElem> vecRegElemClassOps(NumVecElemPerVecReg);
+TypedRegClassOps<ArmISA::VecRegContainer> vecRegClassOps;
+TypedRegClassOps<ArmISA::VecPredRegContainer> vecPredRegClassOps;
 
 ISA::ISA(const Params &p) : BaseISA(p), system(NULL),
     _decoderFlavor(p.decoderFlavor), pmu(p.pmu), impdefAsNop(p.impdef_nop),
@@ -88,10 +90,12 @@ ISA::ISA(const Params &p) : BaseISA(p), system(NULL),
 {
     _regClasses.emplace_back(NUM_INTREGS, INTREG_ZERO);
     _regClasses.emplace_back(0);
-    _regClasses.emplace_back(NumVecRegs, -1, sizeof(VecRegContainer));
+    _regClasses.emplace_back(NumVecRegs, vecRegClassOps, -1,
+            sizeof(VecRegContainer));
     _regClasses.emplace_back(NumVecRegs * NumVecElemPerVecReg,
             vecRegElemClassOps);
-    _regClasses.emplace_back(NumVecPredRegs, -1, sizeof(VecPredRegContainer));
+    _regClasses.emplace_back(NumVecPredRegs, vecPredRegClassOps, -1,
+            sizeof(VecPredRegContainer));
     _regClasses.emplace_back(NUM_CCREGS);
     _regClasses.emplace_back(NUM_MISCREGS, miscRegClassOps);