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Author SHA1 Message Date
Luming Wang
332ef131dc scons: fix build failed caused by Non-ASCII directory path 
This patch addresses the issue of gem5 failing to build when
the build directory path contains non-ASCII characters.
The previous patches[1] that attempted to fix this issue
became ineffective after the upgrade of Python and pybind11
to new versions. This new patch manually sets the locale in
marshal.py based on the `LC_CTYPE` environment variable,
providing a comprehensive solution that works with Non-ASCII
build directory paths.

[1] https://gem5-review.googlesource.com/c/public/gem5/+/58369

Change-Id: I3ad28b6ee52fd347d2fe71f279baab629e88d12c
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70818
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
 2023-05-23 07:24:59 +00:00
Giacomo Travaglini
7b91521c60 arch-arm: Define a AA64ZFR0 data type 
Change-Id: I6b0dcf0c1882f356783934f625c2bc3a25fbb885
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70725
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
 2023-05-23 06:43:21 +00:00
Giacomo Travaglini
3787ab5b20 arch-arm: Rename AdvSIMD instruction pool 
The decoding function was wrongly named decodeNeon3SameExtra,
referring to the "AdvSIMD three same Extra" instruction pool

This might be an old name as I can only find the
"AdvSIMD *scalar* three same Extra" in the Arm arm. The
encoding space reserved to the pool bears the
"Advanced SIMD three-register extension" name; we
therefore rename the function to decodeNeon3RegExtension

Change-Id: I056da8f0c7808935d12a4b05490d30654178071f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70724
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
 2023-05-23 06:43:21 +00:00
Giacomo Travaglini
ae115fcfd5 arch-arm: Implement FEAT_IDST 
Change-Id: I3cabcfdb10f4eefaf2ab039376d840cc4c54609a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70723
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
 2023-05-23 06:43:21 +00:00
Giacomo Travaglini
e005e6f250 arch-arm: Implement trapping of SME registers 
Change-Id: Ic5bcc79a535c928265fbc1db1cd0c85ba1a1b152
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70722
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
 2023-05-23 06:43:21 +00:00
Giacomo Travaglini
1629ee71c7 arch-arm: Implement FEAT_RNG 
Change-Id: I9d60d249172ef4bbaf5d9b38ef279eff344b80d8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70721
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
 2023-05-23 06:43:21 +00:00
Giacomo Travaglini
2a5c427c5c arch-arm: Extend SCR to be 64-bit wide 
Change-Id: I9928de3db61957404269d189a15a951fd6707c8a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70720
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
 2023-05-23 06:43:21 +00:00
Giacomo Travaglini
e3d2191b73 arch-arm: Implement FEAT_FLAGM(2) 
Change-Id: I21f1eb91ad9acb019a776a7d5edd38754571a62e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70719
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2023-05-23 06:43:21 +00:00
Giacomo Travaglini
223a07031f arch-arm: Improve debugging of CC regs accesses 
As of now we are simply printing the CC reg index which is
not particularly helpful. With this patch we actually print
the (NZ|C|V) reg name.

Change-Id: Ib4b56a372b25e5bc2b6b762d2ef3ff2084097cce
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70718
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2023-05-23 06:43:21 +00:00
Giacomo Travaglini
3b3911f521 arch-arm: Split decodeDataProcReg into subfunctions 
This will increase readibility, it will make it easier
for devs to add new instructions, and it removes some
duplication (some register indexes were read more than
once)

Change-Id: Ifa03a93cb73de0b2dc93d7784f9011e0e55dfc1e
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70717
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2023-05-23 06:43:21 +00:00
Giacomo Travaglini
98821e365c arch-arm: Extend auxiliary vector with AT_HWCAP2 entry 
The presence of some of the new extensions is reported via
the AT_HWCAP2 entry

Change-Id: I7a2d813ea84bf528b1f9df09121f9e97456a11c0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70760
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
 2023-05-23 06:43:21 +00:00
Giacomo Travaglini
a3cae50401 arch-arm: Enable FEAT_PAuth in SE mode 
It was in theory already possible to use FEAT_PAuth instructions in
SE mode, however its presence was hidden to userspace code as
the cpu feature was not listed in the auxiliary vectors

Change-Id: I6da5da0878dde56c22ffdba25eff15e36f5022fe
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70759
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2023-05-23 06:43:21 +00:00
Giacomo Travaglini
00426eea99 arch-arm: Define remaining fields of the arm64 AT_HWCAP entry 
Change-Id: I4db4884d677f6d25417ae6edceb7f1e8dfad36cb
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70758
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2023-05-23 06:43:21 +00:00
Bobby R. Bruce
4198d027ac tests,systemc: Fix nightly systemc test 
This fixes these nightly failing tests:
https://jenkins.gem5.org/job/nightly/609/

Due to this commit:
https://gem5-review.googlesource.com/c/public/gem5/+/68758
The source files are not copied to the "build" directory by default.
This caused the systemc tests to fail as the
"util/systemc/gem5_within_systemc/Makefile" depends on generated source
files in the "build" directory.

This patch adds the "--duplicate-sources" flag to the building of the
ARM binaries necessisary for running systemc. The README has been
updated to reflect this.

Change-Id: I3006005e43276097be98f7d4685f3d98c180d3f9
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70860
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
 2023-05-23 03:14:55 +00:00
Roger Chang
9c0f337d78 arch-riscv: Simplify amd merge RV32/RV64 the RVM instructions 
The change move the details implementation to utility.hh and merge
the RV32 and RV64 versions into one.

Change-Id: I438bfb0fc511f0f27e83f247d386c58493db65b4
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70597
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Yu-hsin Wang <yuhsingw@google.com>
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
 2023-05-23 02:34:09 +00:00
Matthew Poremba
08644a7670 dev-amdgpu: Fix nbio psp ring assert 
The size of the packet changes between ROCm 4.x and ROCm 5.x. Change how
the address is set based on the incoming packet size so that both
versions continue to work for now.

Change-Id: I91694e4760198fd9129e60140df4e863666be2e2
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70677
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
 2023-05-22 15:08:11 +00:00
Ayaz Akram
44919c1c4d configs: Update riscv/fs_linux.py script 
This change fixes a couple of small issues with
the configs/example/riscv/fs_linux.py script to ensure
that it works with the latest version of gem5.

Change-Id: I9753ca4c8dd0b87d05681b167cf51e3c097e9152
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70177
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Alex Richardson <alexrichardson@google.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Roger Chang <rogerycchang@google.com>
 2023-05-21 23:56:01 +00:00
Bobby R. Bruce
c4d61ca143 tests: Add '--duplicate-sources' to libgem5 SST build 
Unfortunately the building of SST (in "ext/sst") depends on generated
header files. Therefore it adds the build directory to the include path.
For this to work the libgem5.so must be build with
"--duplicate-sources".

Change-Id: I5ed26a89c81402d421f5dfa110de7cf758f28694
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70497
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2023-05-17 17:49:48 +00:00
Alex Richardson
fccd13ac85 scons: default to not duplicating sources in the build directory 
We now default to --no-duplicate-sources, but keep --duplicate-sources to
opt-out of this new build behaviour in case it introduces regressions.

Change-Id: I2f01ceaef7b6b9bff80f4402081f007110f7e6f3
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/68758
Maintainer: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>
 2023-05-17 17:49:48 +00:00
Bobby R. Bruce
bc63da39dc arch-riscv: Fix WFI for O3 CPU 
This commit:
https://gem5-review.googlesource.com/c/public/gem5/+/61511
introduced a bug where the O3 CPU hangs. This is because WFI must be
tagged as `IsNonSpeculative`, `IsQuiesce`, and `IsSerializeAfter` to
function correctly with O3 CPUs.

Change-Id: I8b6cb049710d05f37f89a9ce22acc604112bc445
Issue-on: https://gem5.atlassian.net/browse/GEM5-1323
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70657
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Roger Chang <rogerycchang@google.com>
Reviewed-by: Jui-min Lee <fcrh@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2023-05-17 17:49:01 +00:00
Giacomo Travaglini
aff1ddb196 arch-arm: Implement FEAT_TLBIOS 
This feature is mandatory in Armv8.4
We are currently not distinguishing Inner and Outer domains.
We therefore implement TLBIOS instructions as TLBIIS

Change-Id: I2198e6155f1eea7c5f8083c6ffb178d3a3d163d3
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70567
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
 2023-05-17 08:11:06 +00:00
Giacomo Travaglini
20bf5e17e3 arch-arm: Extend SCTLR to be 64-bit wide 
In AArch64 SCTLR_EL1/_EL2/_EL3 is 64-bit wide

Change-Id: I80931f9dd1a57f3132229b84d32a8ab08eee3371
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70566
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
 2023-05-17 08:11:06 +00:00
Giacomo Travaglini
60dd3c7d05 arch-arm: Simplify FPSCR writes 
The old logic was setting up a mask which was covering pretty much
the entire register, except for the FPSCR[14:13] and FPSCR[6:5]
register fields. Those RES0 fields were treated as WI.
We simplify this by explicitly marking them as RES0 at construction
time

Change-Id: I59942bd98c074349307d27e3a99351ee25f4db95
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70565
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2023-05-17 08:11:06 +00:00
Giacomo Travaglini
3e1b9dfc0f arch-arm: Remove unnecessary case in ISA::readMiscReg 
Change-Id: I8b95a75fbfec2626fbe8b455ae9b3f30acda538f
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70564
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2023-05-17 08:11:06 +00:00
Giacomo Travaglini
f72d22cc38 arch-arm: Implement RES0/RES1 with miscreg specifiers 
Change-Id: Ic2caea121e02f63f069f1576760c849bcbdac894
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70563
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2023-05-17 08:11:06 +00:00
Giacomo Travaglini
bc5b00cd2b arch-arm: Group self hosted debug writes in ISA switch 
Change-Id: If9c0675743856b603e7b5ec1898f5cdd650f3ce6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70562
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
 2023-05-17 08:11:06 +00:00
Giacomo Travaglini
32b4ab376c arch-arm: Update MISCREG_DBGDIDR to point to Armv8 debug arch 
Change-Id: I20691ecdaedde6740c706782635b1f9a4491dc51
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70561
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2023-05-17 08:11:06 +00:00
Giacomo Travaglini
7c735d131d arch-arm: Implement RAZ/WI with raz specifier 
Change-Id: I195f042fbeb10c0ca1f9095a0d26e6c213496ee5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70560
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2023-05-17 08:11:06 +00:00
Giacomo Travaglini
c85aa11ad0 arch-arm: Provide default mask for raz/rao helpers 
Rather than forcing raz registers to write something like:

.raz(uint64_t(-1))

we provide a shorter version where if
no bitmask is specified we assume the entire register is
raz/rao. This won't be probably used by rao but I
am striving for symmetry and providing a default won't
probably hurt

Change-Id: I309e345fc8336df3a74474f8f9202bf7e2095b41
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70559
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2023-05-17 08:11:06 +00:00
Giacomo Travaglini
de2503f7ce arch-arm: Move RO values from ISA::read to the reset field 
This is simplyfying the ISA::readMiscReg, and it is stopping
us from recomputing values that won't change throughout the
simulation

Change-Id: I62270cdb59f39b8a143e9554c8beaa8cd15824aa
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70558
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
 2023-05-17 08:11:06 +00:00
Giacomo Travaglini
9ef7be902b arch-arm: Add UNSERIALIZE flag to address cpt compatibility 
This patch is adding the MISCREG_UNSERIALIZE flag to expose
the user to the following checkpoint compatibility problem:

What happens when a checkpoint is restored with a different
architectural configuration?

The current behaviour is to silently restore the checkpoint
and to populate the ISA registers accordingly. However some of
these restored values will be used and some of them will
be actually discarded.

For example the value of the MISCREG_ID_AA64ISAR0_EL1 register
(initially configured at construction time [1]) will be overwritten by
the checkpointed value in ISA::unserialize (checkpointed params win over
current params). On the other hand we "discard" the checkpointed value
for registers handled in the ISA::readMiscReg method (not accessing the
storage) like MISCREG_ID_AA64PFR0_EL1 [2] (current params win over
checkpointed params).

In other words some registers will be unserialized while some others
will discard the checkpointed value in favour of the current
configuration setup. This categorization is currently implicit and it
ultimately depends on whether or not a register read access its storage
(see MISCREG_ID_AA64PFR0_EL1 above).

With this patch we formalize this distinction. We allow the developer to
be explict on which register should not be unserialized and should
instead use the new simulation parameters.

If there is a mismatch between the reset value of such register and
the checkpointed one, we warn the user and we undo the unserialization
for such register.

[1]: https://github.com/gem5/gem5/blob/v22.1.0.0/src/arch/arm/isa.cc#L437
[2]: https://github.com/gem5/gem5/blob/v22.1.0.0/src/arch/arm/isa.cc#L1019

Change-Id: Icea6563ee5816b14a097926b5734f2fce10530c7
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70557
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2023-05-17 08:11:06 +00:00
Giacomo Travaglini
5c60160f3e arch-arm: Fix position of AA64ISAR0.AES bitfield 
The bitfield was wrongly [1] placed in the LSBs of the register

[1]: https://developer.arm.com/documentation/ddi0601/2022-03/\
    AArch64-Registers/\
    ID-AA64ISAR0-EL1--AArch64-Instruction-Set-Attribute-Register-0

Change-Id: I577a79e16931a0e1334a9b24459553e2899341f0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70637
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2023-05-16 11:29:55 +00:00
Yan Lee
48ae255762 sim,python: add activate option and method 
With --debug-activate option, user can add the target names into
activate list of debug log.

For example, with "--debug-activate=system.AAA.bus --debug-flags=IOXBar"
We can enable the logs of a specified bus.

Change-Id: I89ce87d784ae9736708bbc976a6bad58732bd5da
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70618
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
 2023-05-16 09:02:38 +00:00
Yan Lee
b923cbe840 base: add Activate to enable log of particular targets 
When the activate list is not empty, only the target name in the list
will be enabled on logging. Even if the target name is in the activate
list, it will need to enable the flag with --debug-flags to enable the
log correctly.

Change-Id: Ic41cb97c8a2530fdc01e954d6cab76ae475d8722
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70617
Reviewed-by: Bobby Bruce <bbruce@ucdavis.edu>
Reviewed-by: Daniel Carvalho <odanrc@yahoo.com.br>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
 2023-05-16 09:02:38 +00:00
Matthew Poremba
ae7476bcdc arch-gcn3,arch-vega: Fix ds_read2st64_b32 
This instruction has two issues. The first is that it should write two
consecutive registers, starting with vdst because it is writing two
dwords. The second is that the data assignment to the lanes from the
dynamic instruction should cast to a U32 type otherwise the array index
goes out of bounds and returns the wrong data.

The first issue was fixed in GCN3 a few years ago in this review:
https://gem5-review.googlesource.com/c/public/gem5/+/32236. This
changeset makes the same change for Vega and applies the U32 cast in
both ISAs.

Tested with rocPRIM unit test. The test was failing before this
changeset and now passes.

Change-Id: Ifb110fc9a36ad198da7eaf86b1e3e37eccd3bb10
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70577
Maintainer: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2023-05-13 20:09:37 +00:00
Roger Chang
8dac7f572b arch-riscv: Refactor RVC decode flow when funct4==0b1001 and op==C2 
the compressed instruction 0x901e (c.add zero, t2) should be decoded as
"c_add zero, t2" not c_ebreak

Change-Id: Ib2bd4b4d9739aa27ad290ead313e95b11b1727d1
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70358
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2023-05-12 00:01:12 +00:00
Roger Chang
d2aed4f5c5 arch-riscv: Treat RVC HINT as nops rather than trap 
The RVC HINT can be implemented as no-op to ignore them. See the
section 18.7 of RISC-V spec Volume I for more details

Change-Id: I88a62fd5722ac542ecfef5fcb80fef2ce04f010f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70357
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
 2023-05-12 00:01:12 +00:00
Roger Chang
27967a40de arch-riscv: Fix the fflags issue for fcvt_d_w, fcvt_d_wu, fcvt_d_l 
fcvt_d_lu

These instructions use type casting methods to convert integer to
float, so the fflags couldn't trace the event of these. It should
use the function xx_to_f64 to convert from integer to float

Change-Id: Idd87306f0ca47b65d3faf17f249568330f374b72
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70377
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
 2023-05-12 00:01:12 +00:00
Roger Chang
331ef9e82b arch-riscv: Add missing zbkb instructions 
Add the following instructions:
pack
packh
packw

Change-Id: I74730c8132187d9a6eb8fc2389c2c28a8a9516df
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70537
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
 2023-05-12 00:01:12 +00:00
Giacomo Travaglini
0fa843c9cb arch-arm: VMPIDR_EL2 can be used in secure mode as well 
This was some old code still assuming EL2 is not implemented in secure
mode. This is wrong since the introduction of FEAT_SEL2 in gem5

Change-Id: Ie7e112a83e64f33a98885e88504c2d6bc5070218
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70471
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
 2023-05-11 15:24:11 +00:00
Giacomo Travaglini
fbca328487 arch-arm: Remove clear32/64 methods 
Change-Id: I62d2dc0612298fdb4cdc3bf368e080c8ebebe23a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70470
Tested-by: kokoro <noreply+kokoro@google.com>
 2023-05-11 15:24:11 +00:00
Giacomo Travaglini
db47e9f9a1 arch-arm: Remove ISA::initID64 
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I3d03ee15df46fa7d9a9ec439b26e99baf33cbb5e
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70469
Tested-by: kokoro <noreply+kokoro@google.com>
 2023-05-11 15:24:11 +00:00
Giacomo Travaglini
e3db30912e arch-arm: Rewrite ISA::initID64 using BitUnions 
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I3e8c7bdcf86c01eccbd90fccaa2d4306a501ed13
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70468
Tested-by: kokoro <noreply+kokoro@google.com>
 2023-05-11 15:24:11 +00:00
Giacomo Travaglini
b7c16f0dad arch-arm: Remove ISA::initID32 
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I70cce0b9d99ed5fe146e64c6ee55fa8cedf98ac6
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70467
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
 2023-05-11 08:25:24 +00:00
Giacomo Travaglini
7abece9d0f arch-arm: Rewrite ISA::initID32 using BitUnions 
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I38460766bb5ed363b176bc6faca8e770a8a5e4c6
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70466
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
 2023-05-11 08:25:24 +00:00
Giacomo Travaglini
c3769affa4 arch-arm: Move MISCREG init logic from ISA to reset field 
Rather than recomputing the reset value every time a system
reset happens (and the ISA::clear method gets called), we
calculate it once and construction time.

We when simply apply the pre-computed reset value to the miscReg
storage, as implemented by a previous patch [1]

[1]: Change-Id: If352501738729927c1c9b300e5b0b8c27ce41b79

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: Iecffff4878217c38707be4ce7d4746ff95a208b4
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70465
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
 2023-05-11 08:25:24 +00:00
Giacomo Travaglini
ec491446f3 arch-arm: Fix read redirection for MIDR register 
This patch is fixing read redirection for the MIDR register
in the following ways:

1) Is allowing a virtualization of the register (via VPIDR)
even in secure mode (available with FEAT_SEL2)
2) Is extending this logic to the AArch64 version (MIDR_EL1)

It is also rewriting the base logic using Armv8 terminology
(checking the EL rather than the mode as an example).

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I5cf09240206287cab877ea7ff6e46cf823aa8c35
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70464
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2023-05-11 08:25:24 +00:00
Giacomo Travaglini
89483caebd arch-arm: Map CTR_EL0 to AArch32 version 
Change-Id: Ia3e0cafa1bd2a3054b286e79ac378c895d6910e8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70463
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
 2023-05-11 08:25:24 +00:00
Giacomo Travaglini
1aa8f14f2c arch-arm: Map MPIDR_EL1 to AArch32 version 
As of now the mapping is not actually needed:
the MPIDR and MPIDR_EL1 registes are both read using the same helper
(readMPIDR). In the future we could store the getMPIDR result in the
AArch32 version without the need to re-calculate the fix affinity
numbers

Change-Id: Id42d1994cdd1722f07874ffa7364154cf011e00a
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70462
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
 2023-05-11 08:25:24 +00:00
Giacomo Travaglini
9dcafac2e7 arch-arm: Map MIDR_EL1 to AArch32 version 
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: Id3ddc18ebfc296389bed6dc7615899bef83178ea
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70461
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
 2023-05-11 08:25:24 +00:00