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arch-arm: Fix read redirection for MIDR register

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This patch is fixing read redirection for the MIDR register
in the following ways:

1) Is allowing a virtualization of the register (via VPIDR)
even in secure mode (available with FEAT_SEL2)
2) Is extending this logic to the AArch64 version (MIDR_EL1)

It is also rewriting the base logic using Armv8 terminology
(checking the EL rather than the mode as an example).

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: I5cf09240206287cab877ea7ff6e46cf823aa8c35
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70464
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2023-02-03 19:22:44 +01:00
parent 89483caebd
commit ec491446f3
1 changed files with 4 additions and 5 deletions
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9
src/arch/arm/isa.cc
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@@ -864,12 +864,11 @@ ISA::readMiscReg(RegIndex idx)
case MISCREG_ID_AFR0: // not implemented, so alias MIDR
case MISCREG_REVIDR: // not implemented, so alias MIDR
case MISCREG_MIDR:
cpsr = readMiscRegNoEffect(MISCREG_CPSR);
scr = readMiscRegNoEffect(MISCREG_SCR_EL3);
if ((cpsr.mode == MODE_HYP) || isSecure(tc)) {
return readMiscRegNoEffect(idx);
} else {
case MISCREG_MIDR_EL1:
if (currEL() == EL1 && EL2Enabled(tc)) {
return readMiscRegNoEffect(MISCREG_VPIDR);
} else {
return readMiscRegNoEffect(idx);
}
break;
case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI