derek/gem5
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

arch-arm: Map CTR_EL0 to AArch32 version

Browse Source 
Change-Id: Ia3e0cafa1bd2a3054b286e79ac378c895d6910e8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70463
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
This commit is contained in:
Giacomo Travaglini
2023-02-07 10:05:41 +00:00
parent 1aa8f14f2c
commit 89483caebd
1 changed files with 2 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/arch/arm/regs/misc.cc
View File

@@ -3681,7 +3681,8 @@ ISA::initializeMiscRegMetadata()
InitReg(MISCREG_CTR_EL0)
.faultRead(EL0, faultCtrEL0)
.faultRead(EL1, HCR_TRAP(tid2))
.reads(1);
.reads(1)
.mapsTo(MISCREG_CTR);
InitReg(MISCREG_DCZID_EL0)
.reads(1);
InitReg(MISCREG_VPIDR_EL2)