From 89483caebd1c055bbbcc1f4411e12602483b52be Mon Sep 17 00:00:00 2001
From: Giacomo Travaglini <giacomo.travaglini@arm.com>
Date: Tue, 7 Feb 2023 10:05:41 +0000
Subject: [PATCH] arch-arm: Map CTR_EL0 to AArch32 version

Change-Id: Ia3e0cafa1bd2a3054b286e79ac378c895d6910e8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70463
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
---
 src/arch/arm/regs/misc.cc | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 706716eb1c..a31b6dec57 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -3681,7 +3681,8 @@ ISA::initializeMiscRegMetadata()
     InitReg(MISCREG_CTR_EL0)
       .faultRead(EL0, faultCtrEL0)
       .faultRead(EL1, HCR_TRAP(tid2))
-      .reads(1);
+      .reads(1)
+      .mapsTo(MISCREG_CTR);
     InitReg(MISCREG_DCZID_EL0)
       .reads(1);
     InitReg(MISCREG_VPIDR_EL2)