From ec491446f36c5a445243c79abecbb3605fc4f745 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Fri, 3 Feb 2023 19:22:44 +0100 Subject: [PATCH] arch-arm: Fix read redirection for MIDR register This patch is fixing read redirection for the MIDR register in the following ways: 1) Is allowing a virtualization of the register (via VPIDR) even in secure mode (available with FEAT_SEL2) 2) Is extending this logic to the AArch64 version (MIDR_EL1) It is also rewriting the base logic using Armv8 terminology (checking the EL rather than the mode as an example). Signed-off-by: Giacomo Travaglini Change-Id: I5cf09240206287cab877ea7ff6e46cf823aa8c35 Reviewed-by: Richard Cooper Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70464 Maintainer: Jason Lowe-Power Reviewed-by: Jason Lowe-Power Tested-by: kokoro --- src/arch/arm/isa.cc | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index 65d8b97404..da23e0b8ce 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -864,12 +864,11 @@ ISA::readMiscReg(RegIndex idx) case MISCREG_ID_AFR0: // not implemented, so alias MIDR case MISCREG_REVIDR: // not implemented, so alias MIDR case MISCREG_MIDR: - cpsr = readMiscRegNoEffect(MISCREG_CPSR); - scr = readMiscRegNoEffect(MISCREG_SCR_EL3); - if ((cpsr.mode == MODE_HYP) || isSecure(tc)) { - return readMiscRegNoEffect(idx); - } else { + case MISCREG_MIDR_EL1: + if (currEL() == EL1 && EL2Enabled(tc)) { return readMiscRegNoEffect(MISCREG_VPIDR); + } else { + return readMiscRegNoEffect(idx); } break; case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI