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arch-arm: Extend auxiliary vector with AT_HWCAP2 entry

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The presence of some of the new extensions is reported via
the AT_HWCAP2 entry

Change-Id: I7a2d813ea84bf528b1f9df09121f9e97456a11c0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70760
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
This commit is contained in:
Giacomo Travaglini
2023-05-18 10:47:55 +01:00
parent a3cae50401
commit 98821e365c
2 changed files with 69 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

61
src/arch/arm/process.cc
View File

@@ -261,6 +261,62 @@ ArmProcess64::armHwcapImpl() const
return hwcap;
}
uint64_t
ArmProcess64::armHwcapImpl2() const
{
enum ArmCpuFeature : uint64_t
{
Arm_None = 0,
Arm_Dcpodp = 1ULL << 0,
Arm_Sve2 = 1ULL<< 1,
Arm_Sveaes = 1ULL << 2,
Arm_Svepmull = 1ULL << 3,
Arm_Svebitperm = 1ULL << 4,
Arm_Svesha3 = 1ULL << 5,
Arm_Svesm4 = 1ULL << 6,
Arm_Flagm2 = 1ULL << 7,
Arm_Frint = 1ULL << 8,
Arm_Svei8mm = 1ULL << 9,
Arm_Svef32mm = 1ULL << 10,
Arm_Svef64mm = 1ULL << 11,
Arm_Svebf16 = 1ULL << 12,
Arm_I8mm = 1ULL << 13,
Arm_Bf16 = 1ULL << 14,
Arm_Dgh = 1ULL << 15,
Arm_Rng = 1ULL << 16,
Arm_Bti = 1ULL << 17,
Arm_Mte = 1ULL << 18,
Arm_Ecv = 1ULL << 19,
Arm_Afp = 1ULL << 20,
Arm_Rpres = 1ULL << 21,
Arm_Mte3 = 1ULL << 22,
Arm_Sme = 1ULL << 23,
Arm_Sme_I16i64 = 1ULL << 24,
Arm_Sme_F64f64 = 1ULL << 25,
Arm_Sme_I8i32 = 1ULL << 26,
Arm_Sme_F16f32 = 1ULL << 27,
Arm_Sme_B16f32 = 1ULL << 28,
Arm_Sme_F32f32 = 1ULL << 29,
Arm_Sme_Fa64 = 1ULL << 30,
Arm_Wfxt = 1ULL << 31,
Arm_Ebf16 = 1ULL << 32,
Arm_Sve_Ebf16 = 1ULL << 33,
Arm_Cssc = 1ULL << 34,
Arm_Rprfm = 1ULL << 35,
Arm_Sve2p1 = 1ULL << 36,
Arm_Sme2 = 1ULL << 37,
Arm_Sme2p1 = 1ULL << 38,
Arm_Sme_I16i32 = 1ULL << 39,
Arm_Sme_Bi32i32 = 1ULL << 40,
Arm_Sme_B16b16 = 1ULL << 41,
Arm_Sme_F16f16 = 1ULL << 42
};
uint64_t hwcap = 0;
return hwcap;
}
template <class IntType>
void
ArmProcess::argsInit(int pageSize, const RegId &spId)
@@ -284,11 +340,10 @@ ArmProcess::argsInit(int pageSize, const RegId &spId)
if (elfObject) {
if (objFile->getOpSys() == loader::Linux) {
IntType features = armHwcap<IntType>();
//Bits which describe the system hardware capabilities
//XXX Figure out what these should be
auxv.emplace_back(gem5::auxv::Hwcap, features);
auxv.emplace_back(gem5::auxv::Hwcap, armHwcap<IntType>());
auxv.emplace_back(gem5::auxv::Hwcap2, armHwcap2<IntType>());
//Frequency at which times() increments
auxv.emplace_back(gem5::auxv::Clktck, 0x64);
//Whether to enable "secure mode" in the executable

12
src/arch/arm/process.hh
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2012, 2018 ARM Limited
* Copyright (c) 2012, 2018, 2023 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -69,10 +69,18 @@ class ArmProcess : public Process
return static_cast<IntType>(armHwcapImpl());
}
template<class IntType>
IntType
armHwcap2() const
{
return static_cast<IntType>(armHwcapImpl2());
}
/**
* AT_HWCAP is 32-bit wide on AArch64 as well so we can
* safely return an uint32_t */
virtual uint32_t armHwcapImpl() const = 0;
virtual uint64_t armHwcapImpl2() const = 0;
};
class ArmProcess32 : public ArmProcess
@@ -86,6 +94,7 @@ class ArmProcess32 : public ArmProcess
/** AArch32 AT_HWCAP */
uint32_t armHwcapImpl() const override;
uint64_t armHwcapImpl2() const override { return 0; }
};
class ArmProcess64 : public ArmProcess
@@ -99,6 +108,7 @@ class ArmProcess64 : public ArmProcess
/** AArch64 AT_HWCAP */
uint32_t armHwcapImpl() const override;
uint64_t armHwcapImpl2() const override;
};
} // namespace gem5