arch-arm: Implement FEAT_RNG

Change-Id: I9d60d249172ef4bbaf5d9b38ef279eff344b80d8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70721
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

src/arch/arm/ArmSystem.py

@@ -88,6 +88,8 @@ class ArmExtension(ScopedEnum):
         "FEAT_FLAGM",
         # Armv8.5
         "FEAT_FLAGM2",
+        "FEAT_RNG",
+        "FEAT_RNG_TRAP",
         # Armv9.2
         "FEAT_SME",  # Optional in Armv9.2
         # Others
@@ -204,7 +206,11 @@ class Armv84(Armv83):
 
 
 class Armv85(Armv84):
-    extensions = Armv84.extensions + ["FEAT_FLAGM2"]
+    extensions = Armv84.extensions + [
+        "FEAT_FLAGM2",
+        "FEAT_RNG",
+        "FEAT_RNG_TRAP",
+    ]
 
 
 class Armv92(Armv85):

src/arch/arm/isa.cc

@@ -49,6 +49,7 @@
 #include "arch/arm/utility.hh"
 #include "arch/generic/decoder.hh"
 #include "base/cprintf.hh"
+#include "base/random.hh"
 #include "cpu/base.hh"
 #include "cpu/checker/cpu.hh"
 #include "cpu/reg_class.hh"
@@ -596,6 +597,21 @@ ISA::readMiscReg(RegIndex idx)
       case MISCREG_HIFAR: // alias for secure IFAR
         return readMiscRegNoEffect(MISCREG_IFAR_S);
 
+      case MISCREG_RNDR:
+        tc->setReg(cc_reg::Nz, (RegVal)0);
+        tc->setReg(cc_reg::C, (RegVal)0);
+        tc->setReg(cc_reg::V, (RegVal)0);
+        return random_mt.random<RegVal>();
+      case MISCREG_RNDRRS:
+        tc->setReg(cc_reg::Nz, (RegVal)0);
+        tc->setReg(cc_reg::C, (RegVal)0);
+        tc->setReg(cc_reg::V, (RegVal)0);
+        // Note: we are not reseeding
+        // The random number generator already has an hardcoded
+        // seed for the sake of determinism. There is no point
+        // in simulating non-determinism here
+        return random_mt.random<RegVal>();
+
       // Generic Timer registers
       case MISCREG_CNTFRQ ... MISCREG_CNTVOFF:
       case MISCREG_CNTFRQ_EL0 ... MISCREG_CNTVOFF_EL2:

src/arch/arm/process.cc

@@ -318,6 +318,7 @@ ArmProcess64::armHwcapImpl2() const
 
     const AA64ISAR0 isa_r0 = tc->readMiscReg(MISCREG_ID_AA64ISAR0_EL1);
     hwcap |= (isa_r0.ts >= 2) ? Arm_Flagm2 : Arm_None;
+    hwcap |= (isa_r0.rndr >= 1) ? Arm_Rng : Arm_None;
 
     return hwcap;
 }

src/arch/arm/regs/misc.cc

@@ -1057,6 +1057,8 @@ std::unordered_map<MiscRegNum64, MiscRegIndex> miscRegNumToIdx{
     { MiscRegNum64(3, 2, 0, 0, 0), MISCREG_CSSELR_EL1 },
     { MiscRegNum64(3, 3, 0, 0, 1), MISCREG_CTR_EL0 },
     { MiscRegNum64(3, 3, 0, 0, 7), MISCREG_DCZID_EL0 },
+    { MiscRegNum64(3, 3, 2, 4, 0), MISCREG_RNDR },
+    { MiscRegNum64(3, 3, 2, 4, 1), MISCREG_RNDRRS },
     { MiscRegNum64(3, 3, 4, 2, 0), MISCREG_NZCV },
     { MiscRegNum64(3, 3, 4, 2, 1), MISCREG_DAIF },
     { MiscRegNum64(3, 3, 4, 2, 2), MISCREG_SVCR },
@@ -1999,6 +2001,20 @@ faultImpdefUnimplEL1(const MiscRegLUTEntry &entry,
     }
 }
 
+Fault
+faultRng(const MiscRegLUTEntry &entry,
+    ThreadContext *tc, const MiscRegOp64 &inst)
+{
+    const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
+    if (HaveExt(tc, ArmExtension::FEAT_RNG_TRAP) && scr.trndr) {
+        return inst.generateTrap(EL3);
+    } else if (!HaveExt(tc, ArmExtension::FEAT_RNG)) {
+        return inst.undefined();
+    } else {
+        return NoFault;
+    }
+}
+
 }
 
 MiscRegIndex
@@ -3894,6 +3910,7 @@ ISA::initializeMiscRegMetadata()
           isar0_el1.ts = release->has(ArmExtension::FEAT_FLAGM2) ?
               0x2 : release->has(ArmExtension::FEAT_FLAGM) ?
                   0x1 : 0x0;
+          isar0_el1.rndr = release->has(ArmExtension::FEAT_RNG) ? 0x1 : 0x0;
           return isar0_el1;
       }())
       .faultRead(EL1, HCR_TRAP(tid3))
@@ -5400,6 +5417,21 @@ ISA::initializeMiscRegMetadata()
     InitReg(MISCREG_MPAMSM_EL1)
         .allPrivileges().exceptUserMode();
 
+    InitReg(MISCREG_RNDR)
+        .faultRead(EL0, faultRng)
+        .faultRead(EL1, faultRng)
+        .faultRead(EL2, faultRng)
+        .faultRead(EL3, faultRng)
+        .unverifiable()
+        .allPrivileges().writes(0);
+    InitReg(MISCREG_RNDRRS)
+        .faultRead(EL0, faultRng)
+        .faultRead(EL1, faultRng)
+        .faultRead(EL2, faultRng)
+        .faultRead(EL3, faultRng)
+        .unverifiable()
+        .allPrivileges().writes(0);
+
     // Dummy registers
     InitReg(MISCREG_NOP)
       .allPrivileges();

src/arch/arm/regs/misc.hh

@@ -1091,6 +1091,10 @@ namespace ArmISA
         MISCREG_TPIDR2_EL0,
         MISCREG_MPAMSM_EL1,
 
+        // FEAT_RNG
+        MISCREG_RNDR,
+        MISCREG_RNDRRS,
+
         // NUM_PHYS_MISCREGS specifies the number of actual physical
         // registers, not considering the following pseudo-registers
         // (dummy registers), like MISCREG_UNKNOWN, MISCREG_IMPDEF_UNIMPL.
@@ -2760,6 +2764,9 @@ namespace ArmISA
         "tpidr2_el0",
         "mpamsm_el1",
 
+        "rndr",
+        "rndrrs",
+
         "num_phys_regs",
 
         // Dummy registers

src/arch/arm/regs/misc_types.hh

@@ -346,6 +346,7 @@ namespace ArmISA
     EndBitUnion(NSACR)
 
     BitUnion64(SCR)
+        Bitfield<40> trndr;
         Bitfield<21> fien;
         Bitfield<20> nmea;
         Bitfield<19> ease;