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arch-arm: Move MISCREG init logic from ISA to reset field

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Rather than recomputing the reset value every time a system
reset happens (and the ISA::clear method gets called), we
calculate it once and construction time.

We when simply apply the pre-computed reset value to the miscReg
storage, as implemented by a previous patch [1]

[1]: Change-Id: If352501738729927c1c9b300e5b0b8c27ce41b79

Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: Iecffff4878217c38707be4ce7d4746ff95a208b4
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70465
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
This commit is contained in:
Giacomo Travaglini
2023-02-03 15:38:59 +01:00
parent ec491446f3
commit c3769affa4
2 changed files with 55 additions and 62 deletions
Download Patch File Download Diff File Expand all files Collapse all files

61
src/arch/arm/isa.cc
View File

@@ -150,67 +150,6 @@ ISA::clear()
// AArch32 or AArch64
initID64(p);
// Start with an event in the mailbox
miscRegs[MISCREG_SEV_MAILBOX] = 1;
// Separate Instruction and Data TLBs
miscRegs[MISCREG_TLBTR] = 1;
MVFR0 mvfr0 = 0;
mvfr0.advSimdRegisters = 2;
mvfr0.singlePrecision = 2;
mvfr0.doublePrecision = 2;
mvfr0.vfpExceptionTrapping = 0;
mvfr0.divide = 1;
mvfr0.squareRoot = 1;
mvfr0.shortVectors = 1;
mvfr0.roundingModes = 1;
miscRegs[MISCREG_MVFR0] = mvfr0;
MVFR1 mvfr1 = 0;
mvfr1.flushToZero = 1;
mvfr1.defaultNaN = 1;
mvfr1.advSimdLoadStore = 1;
mvfr1.advSimdInteger = 1;
mvfr1.advSimdSinglePrecision = 1;
mvfr1.advSimdHalfPrecision = 1;
mvfr1.vfpHalfPrecision = 1;
miscRegs[MISCREG_MVFR1] = mvfr1;
// Reset values of PRRR and NMRR are implementation dependent
// @todo: PRRR and NMRR in secure state?
miscRegs[MISCREG_PRRR_NS] =
(1 << 19) | // 19
(0 << 18) | // 18
(0 << 17) | // 17
(1 << 16) | // 16
(2 << 14) | // 15:14
(0 << 12) | // 13:12
(2 << 10) | // 11:10
(2 << 8) | // 9:8
(2 << 6) | // 7:6
(2 << 4) | // 5:4
(1 << 2) | // 3:2
0; // 1:0
miscRegs[MISCREG_NMRR_NS] =
(1 << 30) | // 31:30
(0 << 26) | // 27:26
(0 << 24) | // 25:24
(3 << 22) | // 23:22
(2 << 20) | // 21:20
(0 << 18) | // 19:18
(0 << 16) | // 17:16
(1 << 14) | // 15:14
(0 << 12) | // 13:12
(2 << 10) | // 11:10
(0 << 8) | // 9:8
(3 << 6) | // 7:6
(2 << 4) | // 5:4
(0 << 2) | // 3:2
0; // 1:0
if (FullSystem && system->highestELIs64()) {
// Initialize AArch64 state
clear64(p);

56
src/arch/arm/regs/misc.cc
View File

@@ -1,5 +1,5 @@
/*
* Copyright (c) 2010-2013, 2015-2022 Arm Limited
* Copyright (c) 2010-2013, 2015-2023 Arm Limited
* All rights reserved
*
* The license below extends only to copyright in the software and shall
@@ -2155,8 +2155,31 @@ ISA::initializeMiscRegMetadata()
InitReg(MISCREG_FPSCR)
.allPrivileges();
InitReg(MISCREG_MVFR1)
.reset([] () {
MVFR1 mvfr1 = 0;
mvfr1.flushToZero = 1;
mvfr1.defaultNaN = 1;
mvfr1.advSimdLoadStore = 1;
mvfr1.advSimdInteger = 1;
mvfr1.advSimdSinglePrecision = 1;
mvfr1.advSimdHalfPrecision = 1;
mvfr1.vfpHalfPrecision = 1;
return mvfr1;
}())
.allPrivileges();
InitReg(MISCREG_MVFR0)
.reset([] () {
MVFR0 mvfr0 = 0;
mvfr0.advSimdRegisters = 2;
mvfr0.singlePrecision = 2;
mvfr0.doublePrecision = 2;
mvfr0.vfpExceptionTrapping = 0;
mvfr0.divide = 1;
mvfr0.squareRoot = 1;
mvfr0.shortVectors = 1;
mvfr0.roundingModes = 1;
return mvfr0;
}())
.allPrivileges();
InitReg(MISCREG_FPEXC)
.allPrivileges();
@@ -2197,6 +2220,7 @@ ISA::initializeMiscRegMetadata()
InitReg(MISCREG_PMXEVTYPER_PMCCFILTR)
.mutex();
InitReg(MISCREG_SEV_MAILBOX)
.reset(1) // Start with an event in the mailbox
.allPrivileges();
InitReg(MISCREG_TLBINEEDSYNC)
.allPrivileges().exceptUserMode();
@@ -2447,6 +2471,7 @@ ISA::initializeMiscRegMetadata()
InitReg(MISCREG_TCMTR)
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_TLBTR)
.reset(1) // Separate Instruction and Data TLBs
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_MPIDR)
.allPrivileges().exceptUserMode().writes(0);
@@ -2870,6 +2895,19 @@ ISA::initializeMiscRegMetadata()
.banked();
InitReg(MISCREG_PRRR_NS)
.bankedChild()
.reset(
(1 << 19) | // 19
(0 << 18) | // 18
(0 << 17) | // 17
(1 << 16) | // 16
(2 << 14) | // 15:14
(0 << 12) | // 13:12
(2 << 10) | // 11:10
(2 << 8) | // 9:8
(2 << 6) | // 7:6
(2 << 4) | // 5:4
(1 << 2) | // 3:2
0)
.privSecure(!aarch32EL3)
.nonSecure().exceptUserMode();
InitReg(MISCREG_PRRR_S)
@@ -2888,6 +2926,22 @@ ISA::initializeMiscRegMetadata()
.banked();
InitReg(MISCREG_NMRR_NS)
.bankedChild()
.reset(
(1 << 30) | // 31:30
(0 << 26) | // 27:26
(0 << 24) | // 25:24
(3 << 22) | // 23:22
(2 << 20) | // 21:20
(0 << 18) | // 19:18
(0 << 16) | // 17:16
(1 << 14) | // 15:14
(0 << 12) | // 13:12
(2 << 10) | // 11:10
(0 << 8) | // 9:8
(3 << 6) | // 7:6
(2 << 4) | // 5:4
(0 << 2) | // 3:2
0)
.privSecure(!aarch32EL3)
.nonSecure().exceptUserMode();
InitReg(MISCREG_NMRR_S)