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arch-arm: Implement RAZ/WI with raz specifier

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Change-Id: I195f042fbeb10c0ca1f9095a0d26e6c213496ee5
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70560
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2023-02-07 10:03:04 +00:00
parent c85aa11ad0
commit 7c735d131d
2 changed files with 5 additions and 6 deletions
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6
src/arch/arm/isa.cc
View File

@@ -470,12 +470,6 @@ ISA::readMiscReg(RegIndex idx)
return readMiscRegNoEffect(idx);
}
break;
case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI
case MISCREG_JMCR: // Jazelle trivial implementation, RAZ/WI
case MISCREG_JIDR: // Jazelle trivial implementation, RAZ/WI
case MISCREG_AIDR: // AUX ID set to 0
case MISCREG_TCMTR: // No TCM's
return 0;
case MISCREG_CLIDR:
warn_once("The clidr register always reports 0 caches.\n");

5
src/arch/arm/regs/misc.cc
View File

@@ -2505,12 +2505,15 @@ ISA::initializeMiscRegMetadata()
.unimplemented()
.allPrivileges();
InitReg(MISCREG_JIDR)
.raz() // Jazelle trivial implementation, RAZ/WI
.allPrivileges();
InitReg(MISCREG_TEEHBR)
.allPrivileges();
InitReg(MISCREG_JOSCR)
.raz() // Jazelle trivial implementation, RAZ/WI
.allPrivileges();
InitReg(MISCREG_JMCR)
.raz() // Jazelle trivial implementation, RAZ/WI
.allPrivileges();
// AArch32 CP15 registers
@@ -2548,6 +2551,7 @@ ISA::initializeMiscRegMetadata()
.unserialize(0)
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_TCMTR)
.raz() // No TCM's
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_TLBTR)
.reset(1) // Separate Instruction and Data TLBs
@@ -2646,6 +2650,7 @@ ISA::initializeMiscRegMetadata()
InitReg(MISCREG_CLIDR)
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_AIDR)
.raz() // AUX ID set to 0
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_CSSELR)
.banked();