diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 14349b1440..7df8978b00 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -470,12 +470,6 @@ ISA::readMiscReg(RegIndex idx)
             return readMiscRegNoEffect(idx);
         }
         break;
-      case MISCREG_JOSCR: // Jazelle trivial implementation, RAZ/WI
-      case MISCREG_JMCR:  // Jazelle trivial implementation, RAZ/WI
-      case MISCREG_JIDR:  // Jazelle trivial implementation, RAZ/WI
-      case MISCREG_AIDR:  // AUX ID set to 0
-      case MISCREG_TCMTR: // No TCM's
-        return 0;
 
       case MISCREG_CLIDR:
         warn_once("The clidr register always reports 0 caches.\n");
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 960c2befc3..6c5a9ddac9 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -2505,12 +2505,15 @@ ISA::initializeMiscRegMetadata()
       .unimplemented()
       .allPrivileges();
     InitReg(MISCREG_JIDR)
+      .raz() // Jazelle trivial implementation, RAZ/WI
       .allPrivileges();
     InitReg(MISCREG_TEEHBR)
       .allPrivileges();
     InitReg(MISCREG_JOSCR)
+      .raz() // Jazelle trivial implementation, RAZ/WI
       .allPrivileges();
     InitReg(MISCREG_JMCR)
+      .raz() // Jazelle trivial implementation, RAZ/WI
       .allPrivileges();
 
     // AArch32 CP15 registers
@@ -2548,6 +2551,7 @@ ISA::initializeMiscRegMetadata()
       .unserialize(0)
       .allPrivileges().exceptUserMode().writes(0);
     InitReg(MISCREG_TCMTR)
+      .raz() // No TCM's
       .allPrivileges().exceptUserMode().writes(0);
     InitReg(MISCREG_TLBTR)
       .reset(1) // Separate Instruction and Data TLBs
@@ -2646,6 +2650,7 @@ ISA::initializeMiscRegMetadata()
     InitReg(MISCREG_CLIDR)
       .allPrivileges().exceptUserMode().writes(0);
     InitReg(MISCREG_AIDR)
+      .raz() // AUX ID set to 0
       .allPrivileges().exceptUserMode().writes(0);
     InitReg(MISCREG_CSSELR)
       .banked();