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arch-arm: Map MIDR_EL1 to AArch32 version

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Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Change-Id: Id3ddc18ebfc296389bed6dc7615899bef83178ea
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70461
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
This commit is contained in:
Giacomo Travaglini
2023-02-03 19:18:55 +01:00
parent 0d1161c56e
commit 9dcafac2e7
2 changed files with 2 additions and 2 deletions
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1
src/arch/arm/isa.cc
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@@ -334,7 +334,6 @@ ISA::initID32(const ArmISAParams &p)
midr = 0x410fc0f0;
miscRegs[MISCREG_MIDR] = midr;
miscRegs[MISCREG_MIDR_EL1] = midr;
miscRegs[MISCREG_VPIDR] = midr;
miscRegs[MISCREG_ID_ISAR0] = p.id_isar0;

3
src/arch/arm/regs/misc.cc
View File

@@ -3507,7 +3507,8 @@ ISA::initializeMiscRegMetadata()
// AArch64 registers (Op0=1,3);
InitReg(MISCREG_MIDR_EL1)
.allPrivileges().exceptUserMode().writes(0);
.allPrivileges().exceptUserMode().writes(0)
.mapsTo(MISCREG_MIDR);
InitReg(MISCREG_MPIDR_EL1)
.allPrivileges().exceptUserMode().writes(0);
InitReg(MISCREG_REVIDR_EL1)