From 9dcafac2e7ce98408ee68d2317decd7d64f35989 Mon Sep 17 00:00:00 2001 From: Giacomo Travaglini Date: Fri, 3 Feb 2023 19:18:55 +0100 Subject: [PATCH] arch-arm: Map MIDR_EL1 to AArch32 version Signed-off-by: Giacomo Travaglini Change-Id: Id3ddc18ebfc296389bed6dc7615899bef83178ea Reviewed-by: Richard Cooper Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70461 Reviewed-by: Jason Lowe-Power Tested-by: kokoro Maintainer: Jason Lowe-Power --- src/arch/arm/isa.cc | 1 - src/arch/arm/regs/misc.cc | 3 ++- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc index b0a856e4b0..65d8b97404 100644 --- a/src/arch/arm/isa.cc +++ b/src/arch/arm/isa.cc @@ -334,7 +334,6 @@ ISA::initID32(const ArmISAParams &p) midr = 0x410fc0f0; miscRegs[MISCREG_MIDR] = midr; - miscRegs[MISCREG_MIDR_EL1] = midr; miscRegs[MISCREG_VPIDR] = midr; miscRegs[MISCREG_ID_ISAR0] = p.id_isar0; diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc index 4221a15aa6..000124c7ad 100644 --- a/src/arch/arm/regs/misc.cc +++ b/src/arch/arm/regs/misc.cc @@ -3507,7 +3507,8 @@ ISA::initializeMiscRegMetadata() // AArch64 registers (Op0=1,3); InitReg(MISCREG_MIDR_EL1) - .allPrivileges().exceptUserMode().writes(0); + .allPrivileges().exceptUserMode().writes(0) + .mapsTo(MISCREG_MIDR); InitReg(MISCREG_MPIDR_EL1) .allPrivileges().exceptUserMode().writes(0); InitReg(MISCREG_REVIDR_EL1)