diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index b0a856e4b0..65d8b97404 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -334,7 +334,6 @@ ISA::initID32(const ArmISAParams &p)
         midr = 0x410fc0f0;
 
     miscRegs[MISCREG_MIDR] = midr;
-    miscRegs[MISCREG_MIDR_EL1] = midr;
     miscRegs[MISCREG_VPIDR] = midr;
 
     miscRegs[MISCREG_ID_ISAR0] = p.id_isar0;
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index 4221a15aa6..000124c7ad 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -3507,7 +3507,8 @@ ISA::initializeMiscRegMetadata()
 
     // AArch64 registers (Op0=1,3);
     InitReg(MISCREG_MIDR_EL1)
-      .allPrivileges().exceptUserMode().writes(0);
+      .allPrivileges().exceptUserMode().writes(0)
+      .mapsTo(MISCREG_MIDR);
     InitReg(MISCREG_MPIDR_EL1)
       .allPrivileges().exceptUserMode().writes(0);
     InitReg(MISCREG_REVIDR_EL1)