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arch-arm: Fix position of AA64ISAR0.AES bitfield

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The bitfield was wrongly [1] placed in the LSBs of the register

[1]: https://developer.arm.com/documentation/ddi0601/2022-03/\
    AArch64-Registers/\
    ID-AA64ISAR0-EL1--AArch64-Instruction-Set-Attribute-Register-0

Change-Id: I577a79e16931a0e1334a9b24459553e2899341f0
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70637
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
This commit is contained in:
Giacomo Travaglini
2023-05-15 11:42:56 +01:00
parent 48ae255762
commit 5c60160f3e
1 changed files with 1 additions and 1 deletions
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2
src/arch/arm/regs/misc_types.hh
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@@ -123,7 +123,7 @@ namespace ArmISA
Bitfield<19, 16> crc32;
Bitfield<15, 12> sha2;
Bitfield<11, 8> sha1;
Bitfield<3, 0> aes;
Bitfield<7, 4> aes;
EndBitUnion(AA64ISAR0)
BitUnion64(AA64ISAR1)