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arch-riscv: Treat RVC HINT as nops rather than trap

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The RVC HINT can be implemented as no-op to ignore them. See the
section 18.7 of RISC-V spec Volume I for more details

Change-Id: I88a62fd5722ac542ecfef5fcb80fef2ce04f010f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70357
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
This commit is contained in:
Roger Chang
2023-05-08 14:06:21 +08:00
parent 27967a40de
commit d2aed4f5c5
1 changed files with 10 additions and 27 deletions
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37
src/arch/riscv/isa/decoder.isa
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@@ -152,11 +152,9 @@ decode QUADRANT default Unknown::unknown() {
}}, {{
if ((RC1 == 0) != (imm == 0)) {
if (RC1 == 0) {
return std::make_shared<IllegalInstFault>(
"source reg x0", machInst);
} else { // imm == 0
return std::make_shared<IllegalInstFault>(
"immediate = 0", machInst);
// imm != 0 is HINT
} else {
// imm == 0 is HINT
}
}
Rc1_sd = rvSext(Rc1_sd + imm);
@@ -179,10 +177,7 @@ decode QUADRANT default Unknown::unknown() {
0x2: CIOp::c_li({{
imm = sext<6>(CIMM5 | (CIMM1 << 5));
}}, {{
if (RC1 == 0) {
return std::make_shared<IllegalInstFault>(
"source reg x0", machInst);
}
// RC1 == 0 is HINT
Rc1_sd = imm;
}});
0x3: decode RC1 {
@@ -202,10 +197,7 @@ decode QUADRANT default Unknown::unknown() {
default: CIOp::c_lui({{
imm = sext<6>(CIMM5 | (CIMM1 << 5)) << 12;
}}, {{
if (RC1 == 0 || RC1 == 2) {
return std::make_shared<IllegalInstFault>(
"source reg x0", machInst);
}
// RC1 == 0 is HINT
if (imm == 0) {
return std::make_shared<IllegalInstFault>(
"immediate = 0", machInst);
@@ -223,8 +215,7 @@ decode QUADRANT default Unknown::unknown() {
"shmat[5] != 0", machInst);
}
if (imm == 0) {
return std::make_shared<IllegalInstFault>(
"immediate = 0", machInst);
// C.SRLI64, HINT for RV32/RV64
}
// The MSB can never be 1, hence no need to sign ext.
Rp1 = rvZext(Rp1) >> imm;
@@ -237,8 +228,7 @@ decode QUADRANT default Unknown::unknown() {
"shmat[5] != 0", machInst);
}
if (imm == 0) {
return std::make_shared<IllegalInstFault>(
"immediate = 0", machInst);
// C.SRAI64, HINT for RV32/RV64
}
Rp1_sd = rvSext(Rp1_sd) >> imm;
}}, uint64_t);
@@ -306,13 +296,9 @@ decode QUADRANT default Unknown::unknown() {
"shmat[5] != 0", machInst);
}
if (imm == 0) {
return std::make_shared<IllegalInstFault>(
"immediate = 0", machInst);
}
if (RC1 == 0) {
return std::make_shared<IllegalInstFault>(
"source reg x0", machInst);
// C.SLLI64, HINT for RV32/RV64
}
// RC1 == 0 is HINT
Rc1 = rvSext(Rc1 << imm);
}}, uint64_t);
format CompressedLoad {
@@ -375,10 +361,7 @@ decode QUADRANT default Unknown::unknown() {
NPC = rvZext(Rc1);
}}, IsIndirectControl, IsUncondControl);
default: CROp::c_mv({{
if (RC1 == 0) {
return std::make_shared<IllegalInstFault>(
"source reg x0", machInst);
}
// RC1 == 0 is HINT
Rc1 = rvSext(Rc2);
}});
}