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arch-riscv: Fix the fflags issue for fcvt_d_w, fcvt_d_wu, fcvt_d_l

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fcvt_d_lu

These instructions use type casting methods to convert integer to
float, so the fflags couldn't trace the event of these. It should
use the function xx_to_f64 to convert from integer to float

Change-Id: Idd87306f0ca47b65d3faf17f249568330f374b72
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70377
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
This commit is contained in:
Roger Chang
2023-05-08 16:18:48 +08:00
parent 331ef9e82b
commit 27967a40de
1 changed files with 12 additions and 4 deletions
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16
src/arch/riscv/isa/decoder.isa
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@@ -2069,22 +2069,30 @@ decode QUADRANT default Unknown::unknown() {
0x69: decode CONV_SGN {
0x0: fcvt_d_w({{
RM_REQUIRED;
Fd = (double)Rs1_sw;
freg_t fd;
fd = freg(i32_to_f64(Rs1_sw));
Fd_bits = fd.v;
}}, FloatCvtOp);
0x1: fcvt_d_wu({{
RM_REQUIRED;
Fd = (double)Rs1_uw;
freg_t fd;
fd = freg(ui32_to_f64(Rs1_uw));
Fd_bits = fd.v;
}}, FloatCvtOp);
0x2: decode RVTYPE {
0x1: fcvt_d_l({{
RM_REQUIRED;
Fd = (double)Rs1_sd;
freg_t fd;
fd = freg(i64_to_f64(Rs1_sd));
Fd_bits = fd.v;
}}, FloatCvtOp);
}
0x3: decode RVTYPE {
0x1: fcvt_d_lu({{
RM_REQUIRED;
Fd = (double)Rs1;
freg_t fd;
fd = freg(ui64_to_f64(Rs1));
Fd_bits = fd.v;
}}, FloatCvtOp);
}
}